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1. 发明授权

US09575923B2 Input/output interface 有权
标题翻译：输入/输出接口
公开(公告)号：US09575923B2
公开(公告)日：2017-02-21
申请号：US14818586
申请日：2015-08-05
申请人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
发明人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
IPC分类号： H03K19/003 , G06F13/42 , H03K19/00 , G05F1/625
CPC分类号： G06F13/16 , G05F1/625 , G06F1/3287 , G06F13/4068 , G06F13/4221 , H03K19/0005 , Y02D10/14 , Y02D10/151
摘要： A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
摘要翻译：操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

2. 发明授权

US09338118B2 Apparatus and method for transmitting push notification message 有权
标题翻译：发送推送通知消息的装置和方法
公开(公告)号：US09338118B2
公开(公告)日：2016-05-10
申请号：US13435884
申请日：2012-03-30
申请人： Jung-Hwan Choi , Hee Seo , Ka-Ram Ko , In-Gyu Kim
发明人： Jung-Hwan Choi , Hee Seo , Ka-Ram Ko , In-Gyu Kim
IPC分类号： G06F15/173 , H04L12/58
CPC分类号： H04L51/30 , H04L51/38
摘要： Provided is an apparatus and method for transmitting a push notification message. To this end, connection is performed with a mobile terminal, and if a push notification message is received from a push notification service providing server, the received push notification message is transmitted to the mobile terminal, and when disconnected from the mobile terminal, a push notification message received after the disconnection is stored, such that transmission of the push notification message can be guaranteed.
摘要翻译：提供了一种用于发送推送通知消息的装置和方法。为此，与移动终端进行连接，如果从推送通知服务提供服务器接收到推送通知消息，则将接收到的推送通知消息发送到移动终端，并且当与移动终端断开连接时，推送在断开连接之后接收的通知消息被存储，使得能够保证推送通知消息的发送。

3. 发明授权

US09269457B2 Semiconductor device capable of rescuing defective characteristics occurring after packaging 有权
公开(公告)号：US09269457B2
公开(公告)日：2016-02-23
申请号：US13777428
申请日：2013-02-26
申请人： Jeong-kyoum Kim , Seok-hun Hyun , Jung-hwan Choi , Seong-jin Jang
发明人： Jeong-kyoum Kim , Seok-hun Hyun , Jung-hwan Choi , Seong-jin Jang
IPC分类号： G11C29/00 , G11C29/04 , G11C29/44 , G11C5/04 , G11C11/40
CPC分类号： G11C17/18 , G11C5/04 , G11C11/40 , G11C17/16 , G11C29/04 , G11C29/44 , G11C29/76 , G11C29/78 , G11C29/789 , G11C2029/4402
摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

4. 发明授权

US08842745B2 Transmission unit adopting a differential voltage driving system, transmission unit and receiving unit selectively adopting a differential current driving system, differential voltage driving system, and interface system 有权
标题翻译：采用差分电压驱动系统的传输单元，选择采用差动电流驱动系统的传输单元和接收单元，差分电压驱动系统和接口系统
公开(公告)号：US08842745B2
公开(公告)日：2014-09-23
申请号：US13142409
申请日：2009-12-03
申请人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
发明人： Ju-Pyo Hong , Jun-Ho Kim , Jung-Hwan Choi
IPC分类号： H04L27/00 , H04L25/02 , H04L7/00 , H03K19/0175 , H04L7/04
CPC分类号： H04L25/0272 , H03K19/017581 , H04L7/0091 , H04L7/041 , H04L25/0282
摘要： In the transmitter, receiver and interface system capable of selective adoption of a differential current driving scheme and a differential voltage driving scheme, a differential current driving scheme and a differential voltage driving scheme can be selectively adopted in one semiconductor chip depending upon the states of the transmission lines, so that effective data transmission is possible and common parts can be shared, whereby a design time can be shortened and a layout area can be reduced.
摘要翻译：在能够选择性地采用差分电流驱动方案和差分电压驱动方案的发射器，接收器和接口系统中，可以在一个半导体芯片中选择性地使用差分电流驱动方案和差分电压驱动方案，这取决于传输线，使得有效的数据传输是可能的，并且可以共享公共部分，从而可以缩短设计时间并且可以减少布局面积。

5. 发明授权

US08797812B2 Memory system having delay-locked-loop circuit 有权
标题翻译：具有延迟锁定环路的存储器系统
公开(公告)号：US08797812B2
公开(公告)日：2014-08-05
申请号：US14185412
申请日：2014-02-20
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C8/00 , G11C7/22 , G11C11/4076 , G11C7/10
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

6. 发明授权

US08358547B2 Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit 有权
标题翻译：延迟锁定环电路，具有延迟锁定环路的半导体器件和存储器系统
公开(公告)号：US08358547B2
公开(公告)日：2013-01-22
申请号：US12979814
申请日：2010-12-28
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C8/00
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

7. 发明授权

US08358546B2 Semiconductor device having additive latency 有权
标题翻译：具有附加延迟的半导体器件
公开(公告)号：US08358546B2
公开(公告)日：2013-01-22
申请号：US12945521
申请日：2010-11-12
申请人： Yang-ki Kim , Jung-hwan Choi
发明人： Yang-ki Kim , Jung-hwan Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.
摘要翻译：半导体器件接收对应于存储器访问操作的命令，并在附加等待时间之后执行存储器存取操作。当接收到命令时，加法等待时间开始。该半导体器件包括用于控制时钟信号的相位并输出相位控制的时钟信号的相位控制器，以及用于产生和输出控制信号的控制器，用于使得能够在加法器中的预定时间禁用相位控制器潜伏期

8. 发明申请

US20110037955A1 LASER PROJECTION DISPLAY AND IMAGE DISTORTION CORRECTION METHOD FOR THE SAME 有权
标题翻译：激光投影显示和图像失真校正方法
公开(公告)号：US20110037955A1
公开(公告)日：2011-02-17
申请号：US12989367
申请日：2009-07-20
申请人： Jung Hoon Seo , Jung Hwan Choi , Jae Wook Kwon
发明人： Jung Hoon Seo , Jung Hwan Choi , Jae Wook Kwon
IPC分类号： G03B21/14
CPC分类号： H04N9/3185 , H04N9/3129
摘要： A laser projection display and a method of compensating for image distortion of the same stereoscopic liquid crystal display device having a touch panel and a method for manufacturing the same are disclosed. Herein, the method includes displaying a picture including a red image, a green image, and a blue image, selecting one of the red image, the green image, and the blue image so as to perform pixel alignment of the picture, calculating pixel coordinate values x+dx and y+dy corresponding to the selected image (herein, x represents the x coordinate value prior to alignment, y represents the y coordinate value prior to alignment, dx represents a varied x coordinate value after alignment, and dy represents a varied y coordinate value after alignment), calculating distortion compensation coordinate values X′ and Y′ corresponding to the pixel coordinate values x+dx and y+dy, and mapping the distortion compensation values X′ and Y′, thereby compensating for an image distortion occurring in the selected image.
摘要翻译：公开了一种激光投影显示器和补偿具有触摸面板的相同立体液晶显示装置的图像失真的方法及其制造方法。这里，该方法包括显示包括红色图像，绿色图像和蓝色图像的图像，选择红色图像，绿色图像和蓝色图像之一，以便执行图像的像素对准，计算像素坐标对应于所选择的图像的值x + dx和y + dy（这里，x表示对准前的x坐标值，y表示对准前的y坐标值，dx表示对准后的变化的x坐标值，dy表示计算对准后的y坐标值的变化），计算与像素坐标值x + dx，y + dy对应的失真补偿坐标值X'，Y'，映射失真补偿值X'，Y'，从而补偿图像失真发生在所选图像中。

9. 发明申请

US20100194457A1 DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：延迟锁定环路电路和包括其的半导体存储器件
公开(公告)号：US20100194457A1
公开(公告)日：2010-08-05
申请号：US12686633
申请日：2010-01-13
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.
摘要翻译：延迟锁定环电路包括：延迟锁定环路块，接收外部时钟并产生延迟锁定的内部时钟; 连接到所述延迟锁定环路块并校正所述内部时钟的占空比的占空比校正块; 以及误差检测单元，比较占空比校正块的第一和第二泵输出节点的电压，以检测占空比校正块的操作误差。

10. 发明授权

US07733708B2 Semiconductor memory device, memory system having the same, and swing width control method thereof 有权
标题翻译：半导体存储器件，具有该半导体存储器件的存储器系统及其摆幅宽度控制方法
公开(公告)号：US07733708B2
公开(公告)日：2010-06-08
申请号：US11648606
申请日：2007-01-03
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/4093 , G11C7/1051 , G11C7/1069 , G11C2207/2254
摘要： A semiconductor memory device that may include output drivers, each of which varies a data swing width in response to a correction code, and one or more data swing width control portions. Each of the data swing width control portions may correspond to an output driver, may vary the correction code according to a data swing width of the corresponding output driver to change the data swing width to a correction swing width, and then varies the correction code again to the extent that data of the corresponding output driver are normally transmitted, which may reduce the data swing width.
摘要翻译：一种半导体存储器件，其可以包括输出驱动器，每个输出驱动器响应于校正代码改变数据摆幅宽度，以及一个或多个数据摆幅宽度控制部分。每个数据摆幅宽度控制部分可以对应于输出驱动器，可以根据对应的输出驱动器的数据摆幅宽度改变校正码，以将数据摆幅宽度改变到校正摆幅宽度，然后再次改变校正码在相应的输出驱动器的数据正常传输的程度上，这可能会降低数据摆幅宽度。

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