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1. 发明申请

US20120059984A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120059984A1
公开(公告)日：2012-03-08
申请号：US13209026
申请日：2011-08-12
申请人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
发明人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
IPC分类号： G06F12/10 , G11C7/00 , H01L23/48
CPC分类号： H01L25/18 , G11C5/02 , G11C7/10 , H01L2224/48091 , H01L2225/06544 , H01L2924/00014
摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
摘要翻译：公开了半导体封装。半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。封装接口包括至少第一对端子。每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个通过衬底通孔的堆叠。

2. 发明授权

US08885380B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08885380B2
公开(公告)日：2014-11-11
申请号：US13209026
申请日：2011-08-12
申请人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
发明人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
IPC分类号： G11C5/02 , H01L25/18 , G11C7/10
CPC分类号： H01L25/18 , G11C5/02 , G11C7/10 , H01L2224/48091 , H01L2225/06544 , H01L2924/00014
摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
摘要翻译：公开了半导体封装。半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。封装接口包括至少第一对端子。每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个通过衬底通孔的堆叠。

3. 发明申请

US20120099389A1 MEMORY CIRCUITS, SYSTEMS, AND MODULES FOR PERFORMING DRAM REFRESH OPERATIONS AND METHODS OF OPERATING THE SAME 有权
标题翻译：用于执行DRAM刷新操作的记忆电路，系统和模块及其操作方法
公开(公告)号：US20120099389A1
公开(公告)日：2012-04-26
申请号：US13236972
申请日：2011-09-20
申请人： Chul-woo PARK , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
发明人： Chul-woo PARK , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
IPC分类号： G11C11/402 , G11C29/00 , G11C7/00
CPC分类号： G11C29/808 , G06F2213/0038 , G11C11/40618 , G11C11/40622 , G11C11/40626 , G11C2211/4062
摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
摘要翻译：存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作命令。

4. 发明申请

US20100045491A1 INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US20100045491A1
公开(公告)日：2010-02-25
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M7/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

5. 发明授权

US08588017B2 Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same 有权
标题翻译：用于执行DRAM刷新操作的存储器电路，系统和模块及其操作方法
公开(公告)号：US08588017B2
公开(公告)日：2013-11-19
申请号：US13236972
申请日：2011-09-20
申请人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
发明人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G06F2213/0038 , G11C11/40618 , G11C11/40622 , G11C11/40626 , G11C2211/4062
摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
摘要翻译：存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作命令。

6. 发明授权

US07986251B2 Input/output (IO) interface and method of transmitting IO data 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US07986251B2
公开(公告)日：2011-07-26
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M5/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多条并行数据中的每一条进行编码并产生多条编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

7. 发明授权

US08638621B2 Semiconductor memory device having a hierarchical bit line scheme 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US08638621B2
公开(公告)日：2014-01-28
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/00 , G11C11/419
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

8. 发明申请

US20120230139A1 SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US20120230139A1
公开(公告)日：2012-09-13
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

9. 发明授权

US07928795B2 Semiconductor device for charge pumping 有权
标题翻译：用于电荷泵浦的半导体器件
公开(公告)号：US07928795B2
公开(公告)日：2011-04-19
申请号：US12458533
申请日：2009-07-15
申请人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
发明人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.
摘要翻译：提供一种用于进行电荷泵送的半导体器件。半导体器件可以包括第一泵送单元，第二泵送单元和控制器。第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。控制器可以被配置为控制第一和第二泵送单元。第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。此外，传输单元可以被配置为控制升压电压的输出。

10. 发明授权

US07589580B2 Reference current generating method and current reference circuit 有权
标题翻译：参考电流产生方法和电流参考电路
公开(公告)号：US07589580B2
公开(公告)日：2009-09-15
申请号：US11797865
申请日：2007-05-08
申请人： Ho-suk Lee , Jae-goo Lee , Young-hyun Jun
发明人： Ho-suk Lee , Jae-goo Lee , Young-hyun Jun
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.
摘要翻译：提供了参考电流产生方法和电流参考电路。参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

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