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1. 发明授权

US07404181B1 Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold 有权
标题翻译：当检测到存储器覆盖的频率超过阈值时，切换到可转换代码有效性的可修改代码的原始代码比较
公开(公告)号：US07404181B1
公开(公告)日：2008-07-22
申请号：US11507779
申请日：2006-08-21
申请人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
发明人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
IPC分类号： G06F9/455
CPC分类号： G06F9/3808 , G06F9/3812
摘要： A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.
摘要翻译：将指令从目标指令集转换为主机指令集的方法。在一个实施例中，多个第一目标指令被转换成多个第一主机指令。在翻译之后，确定多个第一目标指令是否已改变。如果确定减慢了计算机系统的操作，则存储第二多个目标指令的副本并与多个第一目标指令进行比较。在比较之后，如果存在不匹配，则多个第一主机指令被无效。根据一个实施例，当确定指示页面包含对多个第一目标指令的至少一个改变时，开始存储，比较和无效。在一个实施例中，确定是通过检查与多个第一目标指令的存储器位置相关联的比特指示符。

2. 发明申请

US20070233961A1 Multi-portioned instruction memory 审中-公开
标题翻译：多分段指令存储器
公开(公告)号：US20070233961A1
公开(公告)日：2007-10-04
申请号：US11395627
申请日：2006-03-31
申请人： John Banning , Guillermo Rozas
发明人： John Banning , Guillermo Rozas
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F9/30145 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/382 , G06F9/3885 , G06F12/0875 , G06F12/0886
摘要： An instruction memory for storing a plurality of instruction bits. A first portion of the instruction memory is for storing a first subset of bits of the plurality of instruction bits. A second portion of the instruction memory is for storing a second subset of bits of the plurality of instruction bits, wherein the second subset of bits is operable to be accessed by an instruction extractor during an instruction extraction earlier than the first subset of bits.
摘要翻译：一种用于存储多个指令位的指令存储器。指令存储器的第一部分用于存储多个指令位的位的第一子集。指令存储器的第二部分用于存储多个指令位的位的第二子集，其中第二比特子集可操作以在指令提取器之前在比第一比特的子集更早的指令提取期间被访问。

3. 发明授权

US06845353B1 Interpage prologue to protect virtual address mappings 有权
标题翻译： Interpage序言保护虚拟地址映射
公开(公告)号：US06845353B1
公开(公告)日：2005-01-18
申请号：US09471447
申请日：1999-12-23
申请人： Robert Bedichek , David Keppel , John Banning
发明人： Robert Bedichek , David Keppel , John Banning
IPC分类号： G06F9/44 , G06F9/455 , G06F9/46 , G06F11/25 , G06F12/04
CPC分类号： G06F9/3017
摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
摘要翻译：在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。

4. 发明授权

US06615300B1 Fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：在动态翻译系统中快速查找间接分支目的地
公开(公告)号：US06615300B1
公开(公告)日：2003-09-02
申请号：US09596279
申请日：2000-06-19
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F906
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的每个条目包括主机指令地址，目标应用程序的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主机处理器的上下文值，最后四个命名的组件构成主机指令地址的标签，以及一个有效的无效位。在基本实施例中，高速缓存是由主处理器存储器芯片的软件分配的软件缓存。

5. 发明申请

US20120036502A1 CONSISTENCY CHECKING FOR TRANSLATED INTRUCTIONS 有权
标题翻译：一致性检查翻译内容
公开(公告)号：US20120036502A1
公开(公告)日：2012-02-09
申请号：US13021609
申请日：2011-02-04
申请人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
发明人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
IPC分类号： G06F9/455
CPC分类号： G06F9/3808 , G06F9/3812
摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
摘要翻译：在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。响应于检测，将目标指令的副本存储在主机存储器中。响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。此外，响应于基于比较的不匹配，主机指令被禁用。

6. 发明授权

US07904891B2 Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur 失效
标题翻译：检查指令不变性以通过将写入操作发生到存储器部分时存储的副本进行比较来执行先前获得的转换代码
公开(公告)号：US07904891B2
公开(公告)日：2011-03-08
申请号：US12177836
申请日：2008-07-22
申请人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
发明人： John Banning , H. Peter Anvin , Robert Bedichek , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
IPC分类号： G06F9/455
CPC分类号： G06F9/3808 , G06F9/3812
摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.
摘要翻译：在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。响应于检测，将目标指令的副本存储在主机存储器中。响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。此外，响应于基于比较的不匹配，主机指令被禁用。

7. 发明授权

US07644210B1 Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：用于在动态翻译系统中使用间接分支目的地的快速查找来从主处理器存储和检索目标程序指令的翻译的方法和系统
公开(公告)号：US07644210B1
公开(公告)日：2010-01-05
申请号：US11524044
申请日：2006-09-19
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的条目具有主机指令地址和标签，其可以包括目标应用的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主处理器的上下文值那个指令。高速缓存可以是由主处理器存储器的软件或与主存储器分离的硬件缓存分配的软件高速缓存。

8. 发明申请

US20100138638A1 SYSTEM AND METHOD OF INSTRUCTION MODIFICATION 有权
标题翻译：系统和方法的指导性修改
公开(公告)号：US20100138638A1
公开(公告)日：2010-06-03
申请号：US12698809
申请日：2010-02-02
申请人： John Banning , Eric Hao , Brett Coon
发明人： John Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

9. 发明授权

US07111096B1 Fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：在动态翻译系统中快速查找间接分支目的地
公开(公告)号：US07111096B1
公开(公告)日：2006-09-19
申请号：US10463233
申请日：2003-06-17
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F9/30 , G06F9/455 , G06F15/00
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的条目具有主机指令地址和标签，其可以包括目标应用的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主处理器的上下文值那个指令。高速缓存可以是由主处理器存储器的软件或与主存储器分离的硬件缓存分配的软件高速缓存。

10. 发明授权

US06363336B1 Fine grain translation discrimination 有权
标题翻译：细粮翻译歧视
公开(公告)号：US06363336B1
公开(公告)日：2002-03-26
申请号：US09417356
申请日：1999-10-13
申请人： John Banning , H. Peter Anvin , Benjamin Gribstad , David Keppel , Alex Klaiber , Paul Serris
发明人： John Banning , H. Peter Anvin , Benjamin Gribstad , David Keppel , Alex Klaiber , Paul Serris
IPC分类号： G06F900
CPC分类号： G06F9/3812 , G06F9/3017 , G06F9/3808 , G06F9/45504 , G06F12/10
摘要： A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.
摘要翻译：一种用于确定对存储器页面的写入是否被定向到已经被转换为将指令从目标指令集转换到主机指令集的计算机中的主机指令的目标指令的方法，包括以下步骤：检测对存储器页面的写入将已经被转换为主机指令的目标指令存储在存储器页面中，检测写入的存储器页面的子区域是否存储已被翻译的目标指令，以及使从寻址的目标指令转换的主机指令无效。

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