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1. 发明授权

US06363336B1 Fine grain translation discrimination 有权
标题翻译：细粮翻译歧视
公开(公告)号：US06363336B1
公开(公告)日：2002-03-26
申请号：US09417356
申请日：1999-10-13
申请人： John Banning , H. Peter Anvin , Benjamin Gribstad , David Keppel , Alex Klaiber , Paul Serris
发明人： John Banning , H. Peter Anvin , Benjamin Gribstad , David Keppel , Alex Klaiber , Paul Serris
IPC分类号： G06F900
CPC分类号： G06F9/3812 , G06F9/3017 , G06F9/3808 , G06F9/45504 , G06F12/10
摘要： A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.
摘要翻译：一种用于确定对存储器页面的写入是否被定向到已经被转换为将指令从目标指令集转换到主机指令集的计算机中的主机指令的目标指令的方法，包括以下步骤：检测对存储器页面的写入将已经被转换为主机指令的目标指令存储在存储器页面中，检测写入的存储器页面的子区域是否存储已被翻译的目标指令，以及使从寻址的目标指令转换的主机指令无效。

2. 发明申请

US20140189659A1 HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYING CODE 有权
标题翻译：二进制翻译自修改代码和交叉修改代码的处理
公开(公告)号：US20140189659A1
公开(公告)日：2014-07-03
申请号：US13997694
申请日：2012-12-27
申请人： Nirajan L. Cooray , David Keppel , Naveen Kumar , Ori Lempel , Michael Neilly , Naveen Neelakantam , H. Peter Anvin , Sebastian Winkel
发明人： Nirajan L. Cooray , David Keppel , Naveen Kumar , Ori Lempel , Michael Neilly , Naveen Neelakantam , H. Peter Anvin , Sebastian Winkel
IPC分类号： G06F9/455
CPC分类号： G06F9/45525
摘要： A processor core includes a processor to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.
摘要翻译：处理器核心包括处理器，用于执行从存储在第一页中的第一指令转换的第一翻译指令。处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。其他实施例被描述为所要求保护的。

3. 发明授权

US07640450B1 Method and apparatus for handling nested faults 有权
公开(公告)号：US07640450B1
公开(公告)日：2009-12-29
申请号：US10980127
申请日：2004-11-01
申请人： H. Peter Anvin , David Keppel
发明人： H. Peter Anvin , David Keppel
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/0778 , G06F11/0793
摘要： Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first amount of state sufficient to handle a first level fault, and responding to a determination of a nested fault by saving an additional amount of state before handling the fault.

4. 发明授权

US06829719B2 Method and apparatus for handling nested faults 有权
标题翻译：处理嵌套故障的方法和装置
公开(公告)号：US06829719B2
公开(公告)日：2004-12-07
申请号：US09822933
申请日：2001-03-30
申请人： H. Peter Anvin , David Keppel
发明人： H. Peter Anvin , David Keppel
IPC分类号： G06F1100
CPC分类号： G06F11/0721 , G06F11/0778 , G06F11/0793
摘要： Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first amount of state sufficient to handle a first level fault, and responding to a determination of a nested fault by saving an additional amount of state before handling the fault.
摘要翻译：一种用于处理嵌套故障的装置和方法，包括以下步骤：确定故障是否是第一级故障，通过保存足以处理第一级故障的第一数量的状态来响应第一级故障的确定，以及响应于在处理故障之前通过保存额外的状态来确定嵌套故障。

5. 发明授权

US5905855A Method and apparatus for correcting errors in computer systems 失效
标题翻译：用于校正计算机系统中的错误的方法和装置
公开(公告)号：US5905855A
公开(公告)日：1999-05-18
申请号：US807542
申请日：1997-02-28
申请人： Alex Klaiber , Robert Bedichek , David Keppel
发明人： Alex Klaiber , Robert Bedichek , David Keppel
IPC分类号： G06F11/28 , G06F11/16 , G06F11/34 , G06F11/36 , G06F11/26
CPC分类号： G06F11/3688 , G06F11/1641
摘要： A computer implemented process for detecting errors in computer systems including the steps of executing sequences of instructions of a software program on each of a reference system and a test system, detecting and recording state of the reference system and the test system at comparable points in the execution of the program, and comparing the detected state of the reference system and the test system at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system and the test system is automatically replayed if a difference in compared state of the systems is detected.
摘要翻译：一种用于检测计算机系统中的错误的计算机实现过程，包括以下步骤：在参考系统和测试系统中的每一个上执行软件程序的指令序列，在参考系统和测试系统的相似点处检测和记录参考系统和测试系统的状态执行程序，以及在包括指令序列的结束的指令序列中的可选择的可比较点处比较检测到的参考系统和测试系统的状态。在特定实施例中，如果检测到系统的比较状态的差异，则在参考系统和测试系统中的每个参考系之间的可选择可比点之间的指令序列的部分的执行被自动重放。

6. 发明授权

US06668287B1 Software direct memory access 有权
标题翻译：软件直接内存访问
公开(公告)号：US06668287B1
公开(公告)日：2003-12-23
申请号：US09464661
申请日：1999-12-15
申请人： Patrick Boyle , David Keppel , Alex Klaiber , Edmund Kelly
发明人： Patrick Boyle , David Keppel , Alex Klaiber , Edmund Kelly
IPC分类号： G06F1320
CPC分类号： G06F13/32
摘要： Apparatus and a method for generating an interrupt when a direct memory access by an I/O device is desired, suspending the operation of the microprocessor in response to the interrupt, placing state of the morph host to a last known correct state in response to the interrupt, determining the memory operation commanded by the I/O device, and utilizing the microprocessor to execute the memory operation commanded by the I/O device.
摘要翻译：当需要I / O设备的直接存储器访问时产生中断的装置和方法，响应于中断暂停微处理器的操作，响应于该中断将状态主机的状态置于最后已知的正确状态中断，确定由I / O设备命令的存储器操作，并利用微处理器执行由I / O设备命令的存储器操作。

7. 发明授权

US07617088B1 Interpage prologue to protect virtual address mappings 有权
标题翻译： Interpage序言保护虚拟地址映射
公开(公告)号：US07617088B1
公开(公告)日：2009-11-10
申请号：US11110085
申请日：2005-01-18
申请人： Robert Bedichek , David Keppel , John Banning
发明人： Robert Bedichek , David Keppel , John Banning
IPC分类号： G06F9/455
CPC分类号： G06F9/3017
摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
摘要翻译：在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。

8. 发明授权

US06845353B1 Interpage prologue to protect virtual address mappings 有权
标题翻译： Interpage序言保护虚拟地址映射
公开(公告)号：US06845353B1
公开(公告)日：2005-01-18
申请号：US09471447
申请日：1999-12-23
申请人： Robert Bedichek , David Keppel , John Banning
发明人： Robert Bedichek , David Keppel , John Banning
IPC分类号： G06F9/44 , G06F9/455 , G06F9/46 , G06F11/25 , G06F12/04
CPC分类号： G06F9/3017
摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
摘要翻译：在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。

9. 发明申请

US20170187587A1 Technologies for inline network traffic performance tracing 审中-公开
公开(公告)号：US20170187587A1
公开(公告)日：2017-06-29
申请号：US14998208
申请日：2015-12-26
申请人： David Keppel , James Dinan , Robert C. Zak
发明人： David Keppel , James Dinan , Robert C. Zak
IPC分类号： H04L12/26 , H04L12/947 , H04L29/06 , H04L12/861
CPC分类号： H04L43/062 , H04L43/028 , H04L43/12 , H04L49/25 , H04L69/22
摘要： Technologies for tracing network performance in a high performance computing (HPC) network include a network computing device configured to receive a network packet from a source endpoint node and store the header and trace data of the received network packet to a trace buffer of the network computing device. The network computing device is further configured to retrieve updated trace data from the trace buffer and update the trace data portion of the network packet to include the retrieved updated trace data from the trace buffer. Additionally, the network computing device is configured to transmit the updated network packet to a target endpoint node, in which the trace data of the updated network packet is usable by the target endpoint node to determine inline performance of the network relative to a flow of the network packet. Other embodiments are described and claimed herein.

10. 发明申请

US20140344596A1 Controlling Power Consumption Of A Processor Using Interrupt-Mediated On-Off Keying 有权
标题翻译：使用中断介入开关键控制处理器的功耗
公开(公告)号：US20140344596A1
公开(公告)日：2014-11-20
申请号：US13894642
申请日：2013-05-15
申请人： David Keppel , Jawad Nasrullah
发明人： David Keppel , Jawad Nasrullah
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括一个逻辑，用于使得至少一个核心根据ON-OFF密钥协议的功率控制周期进行操作，所述功率控制周期包括多个接通时间和多个关闭时间，其中开启和关闭时间变化取决于是否和何时产生中断。描述和要求保护其他实施例。

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