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1. 发明授权

US08549266B2 System and method of instruction modification 有权
标题翻译：指令修改的系统和方法
公开(公告)号：US08549266B2
公开(公告)日：2013-10-01
申请号：US13155291
申请日：2011-06-07
申请人： John P. Banning , Eric Hao , Brett Coon
发明人： John P. Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

2. 发明申请

US20100122067A1 ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR 审中-公开
标题翻译：多功能微处理器中的交叉螺纹指令分配
公开(公告)号：US20100122067A1
公开(公告)日：2010-05-13
申请号：US12690225
申请日：2010-01-20
申请人： John Erik Lindholm , Brett Coon , Simon S. Moy
发明人： John Erik Lindholm , Brett Coon , Simon S. Moy
IPC分类号： G06F9/312
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。如果有多个功能单元可用，则可以并行调度多个指令。

3. 发明申请

US20070130447A1 System and method for processing thread groups in a SIMD architecture 有权
标题翻译：在SIMD架构中处理线程组的系统和方法
公开(公告)号：US20070130447A1
公开(公告)日：2007-06-07
申请号：US11292614
申请日：2005-12-02
申请人： Brett Coon , John Lindholm
发明人： Brett Coon , John Lindholm
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3838 , G06F9/3851 , G06F9/3869 , G06F9/3887
摘要： A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data processing side and by providing multiple execution pipelines, each with multiple data paths. As a result, higher data processing throughput is achieved while an instruction is fetched and issued once per clock. This configuration also allows a large group of threads to be clustered and executed together through the SIMD processor so that greater memory efficiency can be achieved for certain types of operations like texture memory accesses performed in connection with graphics processing.
摘要翻译： SIMD处理器有效利用其硬件资源来实现更高的数据处理吞吐量。 SIMD处理器的有效宽度通过以数据处理侧的速率的一小部分计时SIMD处理器的指令处理侧，并且通过提供多个执行流水线（每个具有多个数据路径）来扩展。因此，在每个时钟获取和发出一个指令的同时实现更高的数据处理吞吐量。该配置还允许通过SIMD处理器将大组线程聚类并一起执行，使得可以针对某些类型的操作（如结合图形处理执行的纹理存储器访问）实现更高的存储器效率。

4. 发明申请

US20050251653A1 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
公开(公告)号：US20050251653A1
公开(公告)日：2005-11-10
申请号：US11167289
申请日：2005-06-28
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

5. 发明授权

US06615300B1 Fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：在动态翻译系统中快速查找间接分支目的地
公开(公告)号：US06615300B1
公开(公告)日：2003-09-02
申请号：US09596279
申请日：2000-06-19
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F906
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的每个条目包括主机指令地址，目标应用程序的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主机处理器的上下文值，最后四个命名的组件构成主机指令地址的标签，以及一个有效的无效位。在基本实施例中，高速缓存是由主处理器存储器芯片的软件分配的软件缓存。

6. 发明授权

US06356615B1 Programmable event counter system 有权
标题翻译：可编程事件计数器系统
公开(公告)号：US06356615B1
公开(公告)日：2002-03-12
申请号：US09417930
申请日：1999-10-13
申请人： Brett Coon , David Keppel , Charles R. Price
发明人： Brett Coon , David Keppel , Charles R. Price
IPC分类号： G07C300
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： Certain events occurring throughout a microprocessor chip are monitored by a counter system (1) containing a number of digital electronic counters (3, 5, 7 & 9) consolidated at a single location on the processor chip. Those events are communicated to the counter system via electrical leads extending to those functional units in the processor responsible for signaling an event occurrence. Under program control, each counter can be selectively connected (11, 13, 15 & 17) to a selected one of the various functional event producing units. By means of selection logic (19, 21, 23 & 25) separate events originating from multiple functional units may be logically combined, whereby the event counted is a Boolean logic combination of multiple underlying events.
摘要翻译：在整个微处理器芯片中发生的某些事件由包含在处理器芯片上的单个位置固结的多个数字电子计数器（3,5,7和9）的计数器系统（1）进行监视。这些事件通过延伸到处理器中的那些功能单元的电引线传送到计数器系统，其负责发信号通知事件。在程序控制下，每个计数器可以被选择性地连接到各种功能事件产生单元中的所选择的一个中（11,13,15和17）。通过选择逻辑（19,21,23和25），可以逻辑地组合源自多个功能单元的单独事件，由此计数的事件是多个基础事件的布尔逻辑组合。

7. 发明授权

US5619666A System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor 失效
标题翻译：用于将非本地指令转换为本机指令并将其组合到最终存储桶中用于在主机处理器上进行处理的系统
公开(公告)号：US5619666A
公开(公告)日：1997-04-08
申请号：US460272
申请日：1995-06-02
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76 , G06F9/315
CPC分类号： G06F9/30101 , C10G1/00 , C10G17/02 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

8. 发明授权

US08117423B1 Pipeline replay support for multicycle operations 有权
标题翻译：管道重播支持多循环操作
公开(公告)号：US08117423B1
公开(公告)日：2012-02-14
申请号：US12042224
申请日：2008-03-04
申请人： Brett Coon , Godfrey D'Souza , Paul Serris
发明人： Brett Coon , Godfrey D'Souza , Paul Serris
IPC分类号： G06F9/00
CPC分类号： G06F9/3865 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action. Applied in a VLIW processor to an atom operation that requires multiple cycles to complete, in which the first part of the operation is permitted to complete and the atom then reasserted, the control information identifies the second assertion of the atom as the second part of a multi-cycle operation.
摘要翻译：在微处理器的指令流水线（3）中断言的指令伴随着控制信息，包括在处理器的控制信息流水线（15）内断言的一组位。控制信息流水线与指令流水线同步，使指令的控制信息与指令同步进行。控制信息可以直接或间接地识别由指令所要求的操作类型，并且如果要以部分执行操作，则指示要执行的部件。手段包括在诸如多个功能执行单元（7）的处理器中，以解释该控制信息并采取适当的动作。将VLIW处理器应用于需要多个周期来完成的原子操作，其中操作的第一部分被允许完成并且原子然后重新生成，控制信息识别原子的第二个断言作为第二部分多循环操作。

9. 发明申请

US20100138638A1 SYSTEM AND METHOD OF INSTRUCTION MODIFICATION 有权
标题翻译：系统和方法的指导性修改
公开(公告)号：US20100138638A1
公开(公告)日：2010-06-03
申请号：US12698809
申请日：2010-02-02
申请人： John Banning , Eric Hao , Brett Coon
发明人： John Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

10. 发明授权

US07685403B1 Pipeline replay support for multi-cycle operations 有权
标题翻译：管道重播支持多循环操作
公开(公告)号：US07685403B1
公开(公告)日：2010-03-23
申请号：US10463820
申请日：2003-06-16
申请人： Brett Coon , Godfrey D'Souza , Paul Serris
发明人： Brett Coon , Godfrey D'Souza , Paul Serris
IPC分类号： G06F15/00
CPC分类号： G06F9/3865 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in to the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action. Applied in a VLIW processor to an atom operation that requires multiple cycles to complete, in which the first part of the operation is permitted to complete and the atom then reasserted, the control information identifies the second assertion of the atom as the second part of a multi-cycle operation.
摘要翻译：在微处理器的指令流水线（3）中断言的指令伴随着控制信息，包括在处理器的控制信息流水线（15）内断言的一组位。控制信息流水线与指令流水线同步，使指令的控制信息与指令同步进行。控制信息可以直接或间接地识别由指令所要求的操作类型，并且如果要以部分执行操作，则指示要执行的部件。手段包括在处理器中，诸如多个功能执行单元（7），以解释该控制信息并采取适当的动作。将VLIW处理器应用于需要多个周期来完成的原子操作，其中操作的第一部分被允许完成并且原子然后重新生成，控制信息识别原子的第二个断言作为第二部分多循环操作。

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