专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06640297B1 Link pipe system for storage and retrieval of sequences of branch addresses 有权
标题翻译：用于存储和检索分支地址序列的链路管道系统
公开(公告)号：US06640297B1
公开(公告)日：2003-10-28
申请号：US09596280
申请日：2000-06-19
申请人： John Banning , Brett Coon , Eric Hao
发明人： John Banning , Brett Coon , Eric Hao
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/30101
摘要： The speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers (3, 5 & 7) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed (9) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed (11) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a “first in, first out” basis.
摘要翻译：通过重叠间接分支指令序列中的延迟来增加流水线处理器中的间接分支指令序列的处理速度。数字处理器的架构被修改为包括链路管道系统，其允许间接分支所需的分支地址序列被写入处理器内的单个位置，并且从处理器中的单个位置读取。链路管道系统包含用于存储各个分支目标地址的多个寄存器（3,5和7）。分支地址的每个写入自动指向（9）到链路管道系统内的各个寄存器，用于存储相应的分支地址; 并且分支地址的每个READ被自动地指向（11）到包含先前未被处理器读取的地址的最早写入的寄存器，从而以“先进先出”的方式检索分支目标地址。

2. 发明申请

US20110238961A1 SYSTEM AND METHOD OF INSTRUCTION MODIFICATION 有权
标题翻译：系统和方法的指导性修改
公开(公告)号：US20110238961A1
公开(公告)日：2011-09-29
申请号：US13155291
申请日：2011-06-07
申请人： John Banning , Eric Hao , Brett Coon
发明人： John Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

3. 发明授权

US07984277B2 System and method of instruction modification 有权
标题翻译：指令修改的系统和方法
公开(公告)号：US07984277B2
公开(公告)日：2011-07-19
申请号：US12698809
申请日：2010-02-02
申请人： John Banning , Eric Hao , Brett Coon
发明人： John Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

4. 发明申请

US20100138638A1 SYSTEM AND METHOD OF INSTRUCTION MODIFICATION 有权
标题翻译：系统和方法的指导性修改
公开(公告)号：US20100138638A1
公开(公告)日：2010-06-03
申请号：US12698809
申请日：2010-02-02
申请人： John Banning , Eric Hao , Brett Coon
发明人： John Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

5. 发明授权

US06615300B1 Fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：在动态翻译系统中快速查找间接分支目的地
公开(公告)号：US06615300B1
公开(公告)日：2003-09-02
申请号：US09596279
申请日：2000-06-19
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F906
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的每个条目包括主机指令地址，目标应用程序的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主机处理器的上下文值，最后四个命名的组件构成主机指令地址的标签，以及一个有效的无效位。在基本实施例中，高速缓存是由主处理器存储器芯片的软件分配的软件缓存。

6. 发明授权

US07111096B1 Fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：在动态翻译系统中快速查找间接分支目的地
公开(公告)号：US07111096B1
公开(公告)日：2006-09-19
申请号：US10463233
申请日：2003-06-17
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F9/30 , G06F9/455 , G06F15/00
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的条目具有主机指令地址和标签，其可以包括目标应用的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主处理器的上下文值那个指令。高速缓存可以是由主处理器存储器的软件或与主存储器分离的硬件缓存分配的软件高速缓存。

7. 发明授权

US07644210B1 Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system 有权
标题翻译：用于在动态翻译系统中使用间接分支目的地的快速查找来从主处理器存储和检索目标程序指令的翻译的方法和系统
公开(公告)号：US07644210B1
公开(公告)日：2010-01-05
申请号：US11524044
申请日：2006-09-19
申请人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
发明人： John Banning , Brett Coon , Linus Torvalds , Brian Choy , Malcolm Wing , Patrick Gainer
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/45504
摘要： Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
摘要翻译：主机处理器对目标应用的间接分支指令的动态转换通过包括高速缓存来提供对主计算机最常使用的翻译的地址的访问来增强，从而最小化访问翻译缓冲器的需要。缓存中的条目具有主机指令地址和标签，其可以包括目标应用的指令的逻辑地址，该指令的物理地址，指令的代码段限制以及与该指令相关联的主处理器的上下文值那个指令。高速缓存可以是由主处理器存储器的软件或与主存储器分离的硬件缓存分配的软件高速缓存。

8. 发明授权

US08549266B2 System and method of instruction modification 有权
标题翻译：指令修改的系统和方法
公开(公告)号：US08549266B2
公开(公告)日：2013-10-01
申请号：US13155291
申请日：2011-06-07
申请人： John P. Banning , Eric Hao , Brett Coon
发明人： John P. Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

9. 发明授权

US07698539B1 System and method of instruction modification 有权
标题翻译：指令修改的系统和方法
公开(公告)号：US07698539B1
公开(公告)日：2010-04-13
申请号：US10672790
申请日：2003-09-26
申请人： John P. Banning , Eric Hao , Brett Coon
发明人： John P. Banning , Eric Hao , Brett Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/3017
摘要： A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
摘要翻译：指令修改的方法和系统。可以获取可以包括多个离散指令的第一机器语言指令。响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。信息可以根据触发模式中概述的细节代替到细分。或者，可以通过逻辑和/或算术运算将信息与段组合。段的修改产生由处理器的单元执行的第二机器语言指令。在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

10. 发明申请

US20070143582A1 System and method for grouping execution threads 审中-公开
标题翻译：用于分组执行线程的系统和方法
公开(公告)号：US20070143582A1
公开(公告)日：2007-06-21
申请号：US11305558
申请日：2005-12-16
申请人： Brett Coon , John Lindholm
发明人： Brett Coon , John Lindholm
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843
摘要： Multiple threads are divided into buddy groups of two or more threads, so that each thread has assigned to it one or more buddy threads. Only one thread in each buddy group actively executes instructions and this allows buddy threads to share hardware resources, such as registers. When an active thread encounters a swap event, such as a swap instruction, the active thread suspends execution and one of its buddy threads begins execution using that thread's private hardware resources and the buddy group's shared hardware resources. As a result, the thread count can be increased without replicating all of the per-thread hardware resources.
摘要翻译：多个线程被分成两个或更多个线程的好友组，使得每个线程已经分配给它一个或多个好友线程。每个伙伴组中只有一个线程主动执行指令，这样可以让好友线程共享硬件资源，如寄存器。当活动线程遇到交换事件（如交换指令）时，活动线程暂停执行，其一个好友线程将使用该线程的私有硬件资源和好友组的共享硬件资源开始执行。因此，可以增加线程计数，而不复制所有的每线程硬件资源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式