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1. 发明授权

US08799840B1 Branch and bound techniques for computation of critical timing conditions 有权
标题翻译：用于计算关键时序条件的分支和绑定技术
公开(公告)号：US08799840B1
公开(公告)日：2014-08-05
申请号：US12371578
申请日：2009-02-14
申请人： Luis Guerra e Silva , Luis Miguel Silveira , Joel Phillips
发明人： Luis Guerra e Silva , Luis Miguel Silveira , Joel Phillips
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a hierarchy of a netlist of a circuit to determine primary inputs and primary outputs of the circuit at an upper level, and internal vertices of the circuit at lower levels between the primary inputs and the primary outputs; forming a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the primary inputs, the internal vertices and the primary outputs to form a plurality of paths of a path space from the primary inputs to the primary outputs; and in response to the timing delay of the plurality of timing delay edges, dynamically pruning paths of the plurality of paths using branch and bound techniques on bounds of timing delay that are a function of one or more circuit parameters to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the primary inputs and the primary outputs. Additionally or alternatively, timing in the circuit may be analyzed to determine a bound of timing delay of the circuit for one or more parameter corners in a parameter space and if the bound of timing delay is worse than a threshold time delay then one or more parameter corners may be pruned from the parameter space using branch and bound techniques.
摘要翻译：在本发明的一个实施例中，公开了一种用于电子电路设计的方法。该方法包括分析电路网表的层次结构，以确定在较高级别的电路的主输入和主输出，以及在主输入和主输出之间的较低电平处的电路的内部顶点; 形成电路的时序图，其包括表示主输入，内部顶点和主输出之间的定时延迟的多个定时延迟边缘，以形成从主输入到主输出的路径空间的多个路径; 并且响应于所述多个定时延迟边缘的定时延迟，使用在定时延迟的边界上的分支和绑定技术来动态地修剪所述多个路径的路径，所述边界是一个或多个电路参数的函数，以将路径空间减小到电路的一个或多个关键定时路径具有主输入和主输出之间的时序延迟的较差情况度量。附加地或替代地，可以分析电路中的定时以确定参数空间中一个或多个参数角的电路的定时延迟的界限，并且如果定时延迟的范围比阈值时间延迟差，则一个或多个参数可以使用分支和绑定技术从参数空间中修剪角。

2. 发明授权

US08245167B1 Branch and bound techniques for computation of critical timing conditions 有权
标题翻译：用于计算关键时序条件的分支和绑定技术
公开(公告)号：US08245167B1
公开(公告)日：2012-08-14
申请号：US12371579
申请日：2009-02-14
申请人： Luis Guerra e Silva , Luis Miguel Silveira , Joel Phillips
发明人： Luis Guerra e Silva , Luis Miguel Silveira , Joel Phillips
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a hierarchy of a netlist of a circuit to determine primary inputs and primary outputs of the circuit at an upper level, and internal vertices of the circuit at lower levels between the primary inputs and the primary outputs; forming a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the primary inputs, the internal vertices and the primary outputs to form a plurality of paths of a path space from the primary inputs to the primary outputs; and in response to the timing delay of the plurality of timing delay edges, dynamically pruning paths of the plurality of paths using branch and bound techniques on bounds of timing delay that are a function of one or more circuit parameters to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the primary inputs and the primary outputs. Additionally or alternatively, timing in the circuit may be analyzed to determine a bound of timing delay of the circuit for one or more parameter corners in a parameter space and if the bound of timing delay is worse than a threshold time delay then one or more parameter corners may be pruned from the parameter space using branch and bound techniques.
摘要翻译：在本发明的一个实施例中，公开了一种用于电子电路设计的方法。该方法包括分析电路网表的层次结构，以确定在较高级别的电路的主输入和主输出，以及在主输入和主输出之间的较低电平处的电路的内部顶点; 形成电路的时序图，其包括表示主输入，内部顶点和主输出之间的定时延迟的多个定时延迟边缘，以形成从主输入到主输出的路径空间的多个路径; 并且响应于所述多个定时延迟边缘的定时延迟，使用在定时延迟的边界上的分支和绑定技术来动态地修剪所述多个路径的路径，所述边界是一个或多个电路参数的函数，以将路径空间减小到电路的一个或多个关键定时路径具有主输入和主输出之间的时序延迟的较差情况度量。附加地或替代地，可以分析电路中的定时以确定参数空间中的一个或多个参数角的电路的定时延迟的界限，并且如果定时延迟的范围比阈值时间延迟差，则一个或多个参数可以使用分支和绑定技术从参数空间中修剪角。

3. 发明授权

US07853910B1 Parasitic effects analysis of circuit structures 有权
标题翻译：电路结构的寄生效应分析
公开(公告)号：US07853910B1
公开(公告)日：2010-12-14
申请号：US11963523
申请日：2007-12-21
申请人： Zhenhai Zhu , Joel Phillips , Zuo-Chang Ye
发明人： Zhenhai Zhu , Joel Phillips , Zuo-Chang Ye
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Method, system, and computer program product for analyzing circuit structures for parasitic effects are provided. Data from a previous parasitic effect analysis of a circuit structure is used to perform parasitic effect analysis on another circuit structure even when the circuit structures are not identical, provided the circuit structures are similar.
摘要翻译：提供了用于分析寄生效应电路结构的方法，系统和计算机程序产品。使用电路结构的先前寄生效应分析的数据用于对另一电路结构进行寄生效应分析，即使电路结构不相同，只要电路结构相似即可。

4. 发明申请

US20070010787A1 Embolic protection device and methods of use 有权
标题翻译：栓塞保护装置及使用方法
公开(公告)号：US20070010787A1
公开(公告)日：2007-01-11
申请号：US11177473
申请日：2005-07-07
申请人： Steven Hackett , Eric Stainbrook , Thomas Janecek , Chad Trembath , Andrew Dusbabek , John Drontle , Joel Phillips , Thomas Ressemann , Kyle Thunstrom , Peter Keith
发明人： Steven Hackett , Eric Stainbrook , Thomas Janecek , Chad Trembath , Andrew Dusbabek , John Drontle , Joel Phillips , Thomas Ressemann , Kyle Thunstrom , Peter Keith
IPC分类号： A61M29/00
CPC分类号： A61B17/22032 , A61M25/005 , A61M25/10181 , A61M2025/0034 , A61M2025/0037 , A61M2205/8225
摘要： An evacuation sheath assembly and method of reducing or removing a blockage within a vessel without permitting embolization of particulate matter is provided. The evacuation sheath assembly includes a first elongate tubular member, having proximal and distal ends and a main lumen configured to be placed in fluid communication with a blood vessel. An expandable member is provided on a distal portion of the tubular member and is configured to form a seal with the blood vessel. The evacuation assembly further includes a second elongate tubular member having proximal and distal ends and an inflation lumen configured to be placed in fluid communication with the expandable member and a gas inflator. The gas inflator includes a high pressure gas source and a mechanism for regulating the pressure of the gas delivered by the gas inflator. The gas inflator is configured to be placed in fluid communication with the proximal end of the inflation lumen in order to provide a regulated pressure gas source for inflating the expandable member. A method of treatment of a blood vessel using the evacuation sheath assembly includes advancing the evacuation sheath assembly into the blood vessel through a guide catheter. The expandable member is inflated to provide form a seal between the blood vessel and the guide catheter and a vacuum is applied to the main lumen of the first elongate tubular member to cause retrograde blood flow and carry fluid into the main lumen of the evacuation sheath assembly.
摘要翻译：提供疏散护套组件以及在不允许颗粒物质栓塞的情况下减少或去除容器内的堵塞的方法。抽真空组件包括第一细长管状构件，其具有近端和远端以及构造成与血管流体连通的主腔。可膨胀构件设置在管状构件的远侧部分上并构造成与血管形成密封。排气组件还包括具有近端和远端的第二细长管状构件和构造成与膨胀构件和气体充气器流体连通的膨胀腔。气体充气机包括高压气体源和用于调节由气体充气机输送的气体的压力的机构。气体充气器被配置成与膨胀腔的近端流体连通，以便提供用于使可膨胀构件膨胀的调节压力气体源。使用排气鞘组件治疗血管的方法包括通过引导导管将排空鞘组件推进到血管中。可膨胀构件被膨胀以在血管和引导导管之间形成密封，并且将真空施加到第一细长管状构件的主腔，以引起逆行血流并将流体携带到排泄鞘组件的主腔内。

5. 发明申请

US20060265680A1 Method and system for chip design using physically appropriate component models and extraction 有权
公开(公告)号：US20060265680A1
公开(公告)日：2006-11-23
申请号：US11437583
申请日：2006-05-19
申请人： Louis Scheffer , Joel Phillips
发明人： Louis Scheffer , Joel Phillips
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.

6. 发明授权

US06349272B1 Method and system for modeling time-varying systems and non-linear systems 失效
标题翻译：用于对时变系统和非线性系统进行建模的方法和系统
公开(公告)号：US06349272B1
公开(公告)日：2002-02-19
申请号：US09545537
申请日：2000-04-07
申请人： Joel Phillips
发明人： Joel Phillips
IPC分类号： G06G1750
CPC分类号： G06F17/5036 , G06F17/13
摘要： A method and system for generating reduced models of systems having a time-varying elements, a non-linear elements or both is provided. The system and method can be utilized with any systems that are capable of being described with non-linear or time-varying differential equations. The method and system are especially useful for automated extraction of reduced models for nonlinear RF blocks, such as mixers and filters, that have a near linear signal path but may contain strongly nonlinear time-varying components. The models have the accuracy of a transistor level nonlinear simulation but are very compact and so can be used in system level simulation and design.
摘要翻译：提供了一种用于生成具有时变元件，非线性元件或两者的简化模型系统的方法和系统。系统和方法可以与能够用非线性或时变微分方程描述的任何系统一起使用。该方法和系统对于具有近似线性信号路径但可能包含强非线性时变分量的非线性RF块（例如混频器和滤波器）的简化模型的自动提取特别有用。该模型具有晶体管级非线性仿真的精度，但非常紧凑，因此可用于系统级仿真和设计。

7. 发明授权

US07035782B2 Method and device for multi-interval collocation for efficient high accuracy circuit simulation 失效
公开(公告)号：US07035782B2
公开(公告)日：2006-04-25
申请号：US09873988
申请日：2001-06-01
申请人： Baolin Yang , Joel Phillips
发明人： Baolin Yang , Joel Phillips
IPC分类号： G06F17/50
CPC分类号： G06F17/13 , G06F17/5036
摘要： A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.

8. 发明授权

US06322586B1 Catheter tip designs and method of manufacture 有权
标题翻译：导管尖端设计和制造方法
公开(公告)号：US06322586B1
公开(公告)日：2001-11-27
申请号：US09480438
申请日：2000-01-10
申请人： Lance A. Monroe , Andrew D. Bicek , Joel Phillips , Joel R. Munsinger , David Sogard
发明人： Lance A. Monroe , Andrew D. Bicek , Joel Phillips , Joel R. Munsinger , David Sogard
IPC分类号： A61F206
CPC分类号： A61M25/0069 , A61F2/95 , A61F2/966 , A61M25/001
摘要： Methods for making a loaded catheter assembly for delivering a self-expanding stent where the self-expanding stent is carried in a compressed state and the compressed stent has an inside diameter smaller than the outside diameter of the catheter distal tip. The methods can utilize catheter sub-assemblies lacking already attached tips or having partially formed distal tips. A stent can be proximally and co-axially slid over the distal end of the catheter shaft and constrained by a retractable sheath disposed co-axially about the compressed stent. The catheter distal tip can be added or more fully formed after the loading of the stent. Some catheters include a preformed distal conical tip held in position by a heat-shrink film. Other catheters have an elastomeric distal tip waist for slipping over and engaging an outward projection on the catheter shaft distal region. Some catheters are adapted to engage catheter shaft distal threaded regions.
摘要翻译：用于制造用于输送自扩张支架的负载导管组件的方法，其中所述自扩张支架被承载在压缩状态，并且所述压缩支架的内径小于所述导管远端尖端的外径。该方法可以利用缺少已经附着的尖端或具有部分形成的远端尖端的导管子组件。支架可以在导管轴的远端上向近侧并且同轴地滑动并且由围绕压缩的支架共轴设置的可缩回护套约束。导管远端尖端可以在支架装载后加入或更完整地形成。一些导管包括通过热收缩膜保持在适当位置的预成型远端锥形尖端。其它导管具有用于滑动并与导管轴远侧区域上的向外突出部接合的弹性体远侧末端腰部。一些导管适于接合导管轴远端螺纹区域。

9. 发明授权

US07996193B2 Method for reducing model order exploiting sparsity in electronic design automation and analysis 失效
标题翻译：减少采用电子设计自动化和分析中稀疏性的模型顺序的方法
公开(公告)号：US07996193B2
公开(公告)日：2011-08-09
申请号：US12106948
申请日：2008-04-21
申请人： Zuochang Ye , Zhenhai Zhu , Joel Phillips
发明人： Zuochang Ye , Zhenhai Zhu , Joel Phillips
IPC分类号： G06F7/60
CPC分类号： G06F17/5036
摘要： A method for reducing the order of system models exploiting sparsity is disclosed. According to one embodiment, a computer-implemented method receives a system model having a first system order. The system model contains a plurality of system nodes, a plurality of system matrices. The system nodes are reordered and a reduced order system is constructed by a matrix decomposition (e.g., Cholesky or LU decomposition) on an expansion frequency without calculating a projection matrix. The reduced order system model has a lower system order than the original system model.
摘要翻译：公开了一种降低利用稀疏性的系统模型的顺序的方法。根据一个实施例，计算机实现的方法接收具有第一系统顺序的系统模型。系统模型包含多个系统节点，多个系统矩阵。系统节点被重新排序，并且通过在扩展频率上的矩阵分解（例如，Cholesky或LU分解）来构造缩减顺序系统，而不计算投影矩阵。降序系统模型具有比原始系统模型更低的系统顺序。

10. 发明申请

US20090265150A1 METHOD FOR REDUCING MODEL ORDER EXPLOITING SPARSITY 失效
标题翻译：减少模型命令开发空间的方法
公开(公告)号：US20090265150A1
公开(公告)日：2009-10-22
申请号：US12106948
申请日：2008-04-21
申请人： ZUOCHANG YE , Zhenhai Zhu , Joel Phillips
发明人： ZUOCHANG YE , Zhenhai Zhu , Joel Phillips
IPC分类号： G06F7/60
CPC分类号： G06F17/5036
摘要： A method for reducing the order of system models exploiting sparsity is disclosed. According to one embodiment, a computer-implemented method receives a system model having a first system order. The system model contains a plurality of system nodes, a plurality of system matrices. The system nodes are reordered and a reduced order system is constructed by a matrix decomposition (e.g., Cholesky or LU decomposition) on an expansion frequency without calculating a projection matrix. The reduced order system model has a lower system order than the original system model.
摘要翻译：公开了一种降低利用稀疏性的系统模型的顺序的方法。根据一个实施例，计算机实现的方法接收具有第一系统顺序的系统模型。系统模型包含多个系统节点，多个系统矩阵。系统节点被重新排序，并且通过在扩展频率上的矩阵分解（例如，Cholesky或LU分解）来构造缩减顺序系统，而不计算投影矩阵。降序系统模型具有比原始系统模型更低的系统顺序。

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