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1. 发明授权

US09520499B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US09520499B2
公开(公告)日：2016-12-13
申请号：US14867423
申请日：2015-09-28
申请人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
发明人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/66795
摘要： Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.

2. 发明申请

US20160020318A1 Semiconductor Device and Method for Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160020318A1
公开(公告)日：2016-01-21
申请号：US14867423
申请日：2015-09-28
申请人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
发明人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.
摘要翻译：提供一种半导体器件及其制造方法。制造半导体器件的方法包括：提供有源鳍片和场绝缘膜，其包括设置在有源鳍片上的第一沟槽; 通过对设置在所述第一沟槽的侧壁和下部的所述场绝缘膜进行第一蚀刻来形成第二沟槽; 通过对设置在所述第二沟槽的侧壁和下部的所述场绝缘膜进行第二蚀刻，在所述场绝缘膜中形成第一区域和第二区域，所述第一区域邻近所述活性鳍片设置，并且具有与第一区域相比，第二区域与有效翅片间隔开，并且具有比第一厚度厚的第二厚度; 并在有源鳍片和场绝缘膜上形成栅极结构。

3. 发明授权

US09043377B2 Montgomery inverse calculation device and method of calculating montgomery inverse using the same 有权
标题翻译：蒙哥马利逆计算装置和计算montgomery逆的方法相同
公开(公告)号：US09043377B2
公开(公告)日：2015-05-26
申请号：US13361329
申请日：2012-01-30
申请人： Young Sik Kim , Kyoung Moon Ahn , Jong Hoon Shin , Sun-Soo Shin , Ji-Su Kang
发明人： Young Sik Kim , Kyoung Moon Ahn , Jong Hoon Shin , Sun-Soo Shin , Ji-Su Kang
IPC分类号： G06F7/38 , G06F5/01 , G06F7/72 , G06F7/48 , G06F7/52 , G06F7/544
CPC分类号： G06F5/01 , G06F7/48 , G06F7/52 , G06F7/544 , G06F7/728
摘要： A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.
摘要翻译：蒙哥马利逆计算装置包括多个寄存器，每个寄存器存储变量的值，存储模数的模数寄存器，对模数执行乘法的乘法器。比较器将存储在每个寄存器中的变量的值与乘法器的输出值进行比较，并产生多个控制信号。响应于至少一个第一控制信号，多个移位器根据至少一个第一控制信号来移位存储在寄存器中的相应寄存器中的值的位，并且商生成块相对于从一些第一控制信号输出的值计算mod 2m的商移位器响应于第二控制信号。计算块响应于至少一个第三控制信号，使用商来计算每个移位器的输出值的更新值。

4. 发明申请

US20120197953A1 MONTGOMERY INVERSE CALCULATION DEVICE AND METHOD OF CALCULATING MONTGOMERY INVERSE USING THE SAME 有权
标题翻译：蒙特卡洛反相计算装置和使用该方法计算单体反演的方法
公开(公告)号：US20120197953A1
公开(公告)日：2012-08-02
申请号：US13361329
申请日：2012-01-30
申请人： Young Sik KIM , Kyoung Moon Ahn , Jong Hoon Shin , Sun-Soo Shin , Ji-Su Kang
发明人： Young Sik KIM , Kyoung Moon Ahn , Jong Hoon Shin , Sun-Soo Shin , Ji-Su Kang
IPC分类号： G06F7/544 , G06F7/48 , G06F7/52 , G06F5/01
CPC分类号： G06F5/01 , G06F7/48 , G06F7/52 , G06F7/544 , G06F7/728
摘要： A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.
摘要翻译：蒙哥马利逆计算装置包括多个寄存器，每个寄存器存储变量的值，存储模数的模数寄存器，对模数执行乘法的乘法器。比较器将存储在每个寄存器中的变量的值与乘法器的输出值进行比较，并产生多个控制信号。响应于至少一个第一控制信号，多个移位器根据至少一个第一控制信号来移位存储在寄存器中的对应寄存器中的值的位，并且商生成块相对于从一些第一控制信号输出的值计算mod 2m的商移位器响应于第二控制信号。计算块响应于至少一个第三控制信号，使用商来计算每个移位器的输出值的更新值。

5. 发明申请

US20140264572A1 METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASK LAYERS 有权
标题翻译：使用硬掩模层形成半导体器件的方法
公开(公告)号：US20140264572A1
公开(公告)日：2014-09-18
申请号：US14165970
申请日：2014-01-28
申请人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
发明人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
IPC分类号： H01L21/308 , H01L29/78 , H01L29/66
CPC分类号： H01L21/3083 , H01L21/31144 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures.
摘要翻译：形成半导体结构的方法可以包括在其上具有在第一方向上延伸的硬掩模层的硅片上形成光刻掩模。可以使用光刻掩模通过硬掩模层将沟槽形成为硅片，其中沟槽沿第二方向延伸，以将硅片分离成在第一方向上端对端延伸的第一和第二鳍结构。由硬掩模层形成的沟槽的一部分可以相对于由第一和第二鳍结构限定的沟槽的下部加宽。

6. 发明授权

US08706788B2 Modular calculator, operation method of the modular calculator, and apparatuses having the same 有权
标题翻译：模块化计算器，模块化计算器的操作方法，以及具有该计算器的装置
公开(公告)号：US08706788B2
公开(公告)日：2014-04-22
申请号：US13241778
申请日：2011-09-23
申请人： Jong Hoon Shin , Kyoung Moon Ahn , Young Sik Kim , Sun-Soo Shin , Ji-Su Kang
发明人： Jong Hoon Shin , Kyoung Moon Ahn , Young Sik Kim , Sun-Soo Shin , Ji-Su Kang
IPC分类号： G06F7/72
CPC分类号： G06F7/72
摘要： A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value.
摘要翻译：提供了一种模块化计算器和一种执行模数计算的方法。模块化计算器包括：第一寄存器，用于接收和存储第一整数;第二寄存器，用于接收和存储第二整数;连接到第一寄存器的输出端的计算器和第二寄存器的输出端，以及控制器通过参考第一整数的符号和第二整数的符号来确定计算器的算术运算，并且控制计算器对第一整数的加法和减法之一执行所确定的算术运算，第二整数和模数值。

7. 发明申请

US20110231467A1 MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE 有权
标题翻译：具有有效硬件结构的蒙特卡罗公司
公开(公告)号：US20110231467A1
公开(公告)日：2011-09-22
申请号：US13052524
申请日：2011-03-21
申请人： Kyoung-moon AHN , Young-sik Kim , Jong-hoon Shin , Sun-soo Shin , Ji-su Kang
发明人： Kyoung-moon AHN , Young-sik Kim , Jong-hoon Shin , Sun-soo Shin , Ji-su Kang
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/728
摘要： A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.
摘要翻译：一个radix-2k蒙哥马利乘数器，其包括用于接收乘法器的输入系数产生单元，乘法器，模数，和和先前和，以通过使用乘法器中的至少一个来产生和输出部分乘积和多重模数，被乘数，模数和和，并且将接收的先前和除以并输出到k位的单位，用于接收部分乘积的累加器电路，来自输入系数生成的先前和的多个模数和k个比特并且通过将部分乘积，多重模量和前一个和相加来产生和输出一个进位和一个和以及一个进位传播加法器（CPA）电路，以通过使用进位和运算来产生和输出最终和和。

8. 发明申请

US20120317159A1 MODULAR OPERATOR, DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF 审中-公开
标题翻译：模块化操作器，具有该操作器的装置及其操作方法
公开(公告)号：US20120317159A1
公开(公告)日：2012-12-13
申请号：US13451815
申请日：2012-04-20
申请人： Kyoung Moon Ahn , Jong Hoon Shin , Ji-Su Kang , Sun-Soo Shin
发明人： Kyoung Moon Ahn , Jong Hoon Shin , Ji-Su Kang , Sun-Soo Shin
IPC分类号： G06F7/48 , G06F5/01
CPC分类号： G06F7/72
摘要： A modular operator, a smart card including the same, and a method of operating the same are provided. The modular operator includes: an input unit configured to receive first data, second data, and a modulus; and an accumulator configured to perform an accumulation operation on the first data and a first portion of the second data, to shift the accumulation operation result to the right as much as the number of bits of the first portion, and to perform an accumulation operation on a result of a shifted accumulation operation, a second part, of the second data, which is shifted to the right as much as the number of bits of the first portion, and the modulus.
摘要翻译：提供了一种模块化操作员，包括其的智能卡及其操作方法。模块化操作员包括：输入单元，被配置为接收第一数据，第二数据和模数; 以及累加器，其被配置为对所述第一数据和所述第二数据的第一部分执行累加操作，以将所述累积运算结果向所述第一部分的比特数的右侧移动，并且对所述累加操作执行累加操作第二数据的移位累积操作的结果，第二数据的第二部分，其被移位到与第一部分的位数一样多的右侧和模数。

9. 发明申请

US20120096062A1 MODULAR CALCULATOR, OPERATION METHOD OF THE MODULAR CALCULATOR, AND APPARATUSES HAVING THE SAME 有权
标题翻译：模块化计算器，模块化计算器的操作方法及其设备
公开(公告)号：US20120096062A1
公开(公告)日：2012-04-19
申请号：US13241778
申请日：2011-09-23
申请人： Jong Hoon SHIN , Kyoung Moon AHN , Young Sik KIM , Sun-Soo SHIN , Ji-Su KANG
发明人： Jong Hoon SHIN , Kyoung Moon AHN , Young Sik KIM , Sun-Soo SHIN , Ji-Su KANG
IPC分类号： G06F7/50
CPC分类号： G06F7/72
摘要： A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value.
摘要翻译：提供了一种模块化计算器和一种执行模数计算的方法。模块化计算器包括：第一寄存器，用于接收和存储第一整数;第二寄存器，用于接收和存储第二整数;连接到第一寄存器的输出端的计算器和第二寄存器的输出端，以及控制器通过参考第一整数的符号和第二整数的符号来确定计算器的算术运算，并且控制计算器对第一整数的加法和减法之一执行所确定的算术运算，第二整数和模数值。

10. 发明申请

US20140357061A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140357061A1
公开(公告)日：2014-12-04
申请号：US14287240
申请日：2014-05-27
申请人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
发明人： Sung-Min Kim , Ji-Su Kang , Dong-Kyu Lee , Dong-Ho Cha
IPC分类号： H01L29/66
CPC分类号： H01L29/785 , H01L29/66795
摘要： Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.
摘要翻译：提供一种半导体器件及其制造方法。制造半导体器件的方法包括：提供有源鳍片和场绝缘膜，其包括设置在有源鳍片上的第一沟槽; 通过对设置在所述第一沟槽的侧壁和下部的所述场绝缘膜进行第一蚀刻来形成第二沟槽; 通过对设置在所述第二沟槽的侧壁和下部的所述场绝缘膜进行第二蚀刻，在所述场绝缘膜中形成第一区域和第二区域，所述第一区域邻近所述活性鳍片设置，并且具有与第一区域相比，第二区域与有效翅片间隔开，并且具有比第一厚度厚的第二厚度; 并在有源鳍片和场绝缘膜上形成栅极结构。

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