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1. 发明授权

US06940129B2 Double gate MOS transistors 失效
标题翻译：双栅MOS晶体管
公开(公告)号：US06940129B2
公开(公告)日：2005-09-06
申请号：US10715664
申请日：2003-11-18
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648 , H01L29/78654
摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.
摘要翻译：双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。顶栅电极与底栅电极重叠并与晶体管有源区绝缘。还提供制造这种晶体管的方法。

2. 发明授权

US07615429B2 Methods of fabricating field effect transistors having multiple stacked channels 有权
标题翻译：制造具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US07615429B2
公开(公告)日：2009-11-10
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

3. 发明授权

US07397131B2 Self-aligned semiconductor contact structures 失效
标题翻译：自对准半导体接触结构
公开(公告)号：US07397131B2
公开(公告)日：2008-07-08
申请号：US11396819
申请日：2006-04-03
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/772
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
摘要翻译：自对准接触结构及其形成方法包括具有相邻侧壁的选定的相邻栅电极，其被配置为朝向彼此成角度。可以使用能够延长接触窗口的长度以限定接触窗的侧壁的衬里层来保护栅电极的成角度的表面。

4. 发明申请

US20080090362A1 METHODS OF FABRICATING FIELD EFFECT TRANSISTORS HAVING MULTIPLE STACKED CHANNELS 有权
标题翻译：制作具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US20080090362A1
公开(公告)日：2008-04-17
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

5. 发明申请

US20060170062A1 Self-aligned semiconductor contact structures and methods for fabricating the same 审中-公开
标题翻译：自对准半导体接触结构及其制造方法
公开(公告)号：US20060170062A1
公开(公告)日：2006-08-03
申请号：US11395270
申请日：2006-03-31
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
摘要翻译：自对准接触结构及其形成方法包括具有相邻侧壁的选定的相邻栅电极，其被配置为朝向彼此成角度。可以使用能够延长接触窗口的长度以限定接触窗的侧壁的衬里层来保护栅电极的成角度的表面。

6. 发明授权

US07071517B2 Self-aligned semiconductor contact structures and methods for fabricating the same 失效
公开(公告)号：US07071517B2
公开(公告)日：2006-07-04
申请号：US10695061
申请日：2003-10-28
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/41
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

7. 发明授权

US07002207B2 Field effect transistors having multiple stacked channels 有权
标题翻译：具有多个堆叠通道的场效应晶体管
公开(公告)号：US07002207B2
公开(公告)日：2006-02-21
申请号：US10610607
申请日：2003-07-01
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。源极/漏极区域在预活化图案的相对端处在衬底上形成。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

8. 发明授权

US07871914B2 Methods of fabricating semiconductor devices with enlarged recessed gate electrodes 有权
标题翻译：制造具有放大的凹陷栅电极的半导体器件的方法
公开(公告)号：US07871914B2
公开(公告)日：2011-01-18
申请号：US12431488
申请日：2009-04-28
申请人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
发明人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.
摘要翻译：半导体器件包括其中具有凹部的半导体衬底。栅极绝缘体设置在凹部中的基板上。该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。源极/漏极区域设置在邻近凹部的衬底中。凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。源极/漏极区域可以包括邻近凹部的较轻掺杂部分。还讨论了相关制造方法。

9. 发明授权

US07541656B2 Semiconductor devices with enlarged recessed gate electrodes 有权
标题翻译：半导体器件具有放大的凹陷栅电极
公开(公告)号：US07541656B2
公开(公告)日：2009-06-02
申请号：US11556352
申请日：2006-11-03
申请人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
发明人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.
摘要翻译：半导体器件包括其中具有凹部的半导体衬底。栅极绝缘体设置在凹部中的基板上。该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。源极/漏极区域设置在邻近凹部的衬底中。凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。源极/漏极区域可以包括邻近凹部的较轻掺杂部分。还讨论了相关制造方法。

10. 发明申请

US20070057288A1 Methods of Fabricating Semiconductor Devices with Enlarged Recessed Gate Electrodes 有权
标题翻译：制造具有放大栅极电极的半导体器件的方法
公开(公告)号：US20070057288A1
公开(公告)日：2007-03-15
申请号：US11556352
申请日：2006-11-03
申请人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
发明人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
IPC分类号： H01L31/00
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.
摘要翻译：半导体器件包括其中具有凹部的半导体衬底。栅极绝缘体设置在凹部中的基板上。该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。源极/漏极区域设置在邻近凹部的衬底中。凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。源极/漏极区域可以包括邻近凹部的较轻掺杂部分。还讨论了相关制造方法。

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