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    • 2. 发明授权
    • Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect
    • 验证设计实体在寄存器传输级别的电源关闭效果的方法以及断电效果建模方法
    • US07415685B2
    • 2008-08-19
    • US11506668
    • 2006-08-18
    • Bong-Il ParkJeong-Joo Lee
    • Bong-Il ParkJeong-Joo Lee
    • G06F17/50G06F17/10
    • G06F17/5022
    • A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for performing predetermined functions using a plurality of power sources. The device model includes a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked. The test input signal model describes a test input signal to be input to the device model to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked. The test output signal model describes a test output signal to be output from the device model in response to the test input signal.
    • 验证数字系统的设计实体的断电效果的方法包括在寄存器传送级(RTL)的硬件设计语言中指定的设备模型,测试输入信号模型和测试输出信号模型。 该设备模型描述了使用多个电源来执行预定功能的功能块。 该装置模型包括用于提供所有电源的情况的模型和用于一个或多个电源被阻塞的情况的模型。 测试输入信号模型描述要输入到设备模型的测试输入信号,以验证所有电源的供电情况以及一个或多个电源被阻塞的情况。 测试输出信号模型描述了响应于测试输入信号从设备模型输出的测试输出信号。
    • 4. 发明申请
    • Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect
    • 验证设计实体在寄存器传输级别的电源关闭效果的方法以及断电效果建模方法
    • US20070044052A1
    • 2007-02-22
    • US11506668
    • 2006-08-18
    • Bong-Il ParkJeong-Joo Lee
    • Bong-Il ParkJeong-Joo Lee
    • G06F17/50
    • G06F17/5022
    • A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for performing predetermined functions using a plurality of power sources. The device model includes a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked. The test input signal model describes a test input signal to be input to the device model to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked. The test output signal model describes a test output signal to be output from the device model in response to the test input signal.
    • 验证数字系统的设计实体的断电效果的方法包括在寄存器传送级(RTL)的硬件设计语言中指定的设备模型,测试输入信号模型和测试输出信号模型。 该设备模型描述了使用多个电源来执行预定功能的功能块。 该装置模型包括用于提供所有电源的情况的模型和用于一个或多个电源被阻塞的情况的模型。 测试输入信号模型描述要输入到设备模型的测试输入信号,以验证所有电源的供电情况以及一个或多个电源被阻塞的情况。 测试输出信号模型描述了响应于测试输入信号从设备模型输出的测试输出信号。