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1. 发明申请

US20050232159A1 Scalable extensible network test architecture 失效
公开(公告)号：US20050232159A1
公开(公告)日：2005-10-20
申请号：US11133073
申请日：2005-05-18
申请人： Jeong Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
发明人： Jeong Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
IPC分类号： G06F1/26 , H04L1/00
CPC分类号： G06F1/189 , G06F1/181 , H04L43/50
摘要： A network test architecture includes a plurality of modules for performing a plurality of functions, each of the plurality of modules having a unique identifier. An additional module for performing an additional function has an additional unique identifier. A control bus is connected among the plurality of modules; a data bus is connected among the plurality of modules; and a power bus is connected among the plurality of modules. A controller controls operation, data transmission, and powering of the plurality of modules and the additional module, respectively, through the control bus, the data bus, and the power bus, the controller using the unique identifier and the additional unique identifier of the plurality of modules upon simultaneous connection of the control bus, the data bus, and the power bus to the additional module.

2. 发明授权

US06898720B2 Scalable extensible network test architecture 有权
标题翻译：可扩展的可扩展网络测试架构
公开(公告)号：US06898720B2
公开(公告)日：2005-05-24
申请号：US10328469
申请日：2002-12-24
申请人： Jeong Eun Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
发明人： Jeong Eun Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/189 , G06F1/181 , H04L43/50
摘要： A network test architecture includes a plurality of modules for performing a plurality of functions, each of the plurality of modules having a unique identifier. An additional module for performing an additional function has an additional unique identifier. A control bus is connected among the plurality of modules; a data bus is connected among the plurality of modules; and a power bus is connected among the plurality of modules. A controller controls operation, data transmission, and powering of the plurality of modules and the additional module, respectively, through the control bus, the data bus, and the power bus, the controller using the unique identifier and the additional unique identifier of the plurality of modules upon simultaneous connection of the control bus, the data bus, and the power bus to the additional module.
摘要翻译：网络测试架构包括用于执行多个功能的多个模块，所述多个模块中的每个模块具有唯一的标识符。用于执行附加功能的附加模块具有附加的唯一标识符。控制总线连接在多个模块之间; 数据总线连接在多个模块之间; 并且多个模块之间连接有电力总线。控制器通过控制总线，数据总线和电源总线分别控制多个模块和附加模块的操作，数据传输和供电，控制器使用唯一标识符和多个的附加唯一标识符的模块，同时将控制总线，数据总线和电源总线连接到附加模块。

3. 发明授权

US07447921B2 Scalable extensible network test architecture 失效
标题翻译：可扩展的可扩展网络测试架构
公开(公告)号：US07447921B2
公开(公告)日：2008-11-04
申请号：US11133073
申请日：2005-05-18
申请人： Jeong Eun Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
发明人： Jeong Eun Joo , Fred King , Patrick Riley , Aart Konynenberg , Paul Chang
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/189 , G06F1/181 , H04L43/50
摘要： A network test architecture includes a plurality of modules for performing a plurality of functions, each of the plurality of modules having a unique identifier. An additional module for performing an additional function has an additional unique identifier. A control bus is connected among the plurality of modules; a data bus is connected among the plurality of modules; and a power bus is connected among the plurality of modules. A controller controls operation, data transmission, and powering of the plurality of modules and the additional module, respectively, through the control bus, the data bus, and the power bus, the controller using the unique identifier and the additional unique identifier of the plurality of modules upon simultaneous connection of the control bus, the data bus, and the power bus to the additional module.
摘要翻译：网络测试架构包括用于执行多个功能的多个模块，所述多个模块中的每个模块具有唯一的标识符。用于执行附加功能的附加模块具有附加的唯一标识符。控制总线连接在多个模块之间; 数据总线连接在多个模块之间; 并且多个模块之间连接有电力总线。控制器通过控制总线，数据总线和电源总线分别控制多个模块和附加模块的操作，数据传输和供电，控制器使用唯一标识符和多个的附加唯一标识符的模块，同时将控制总线，数据总线和电源总线连接到附加模块。

4. 发明授权

US5757652A Electrical signal jitter and wander measurement system and method 失效
标题翻译：电信号抖动和漂移测量系统及方法
公开(公告)号：US5757652A
公开(公告)日：1998-05-26
申请号：US576422
申请日：1995-12-21
申请人： Stephen F. Blazo , Jeffrey A. Kleck , Aart Konynenberg , Philip Schniter
发明人： Stephen F. Blazo , Jeffrey A. Kleck , Aart Konynenberg , Philip Schniter
IPC分类号： G01R29/26 , H03L7/099 , H04L1/20 , H04Q11/04 , H04L7/00
CPC分类号： H03L7/0994 , G01R29/26 , H04L1/205 , H04J2203/0062
摘要： An electrical signal jitter and wander measurement system (30) operates in real time and digitally controls bandwidths over which the measurements are performed. A digital phase-lock loop ("PLL") (34) includes a phase detector (44), low pass filters (48, 56), an analog-to-digital converter ("ADC") (54), a digital signal processor ("DSP") (32), a direct digital synthesizer ("DDS") (38), and a tracking oscillator (39). The phase detector receives an input signal that is compared with a signal derived from the DDS. The phase detector signal contains wander and jitter data that are filtered and digitized by the ADC. The DSP receives the data and performs a proportional integral control function to lock the PLL by digitally controlling the DDS frequency. The DDS generates a clock signal at a precise rate determined by the phase accumulation registers. The tracking oscillator locks to multiples of the DDS frequency to increase the resolution of the phase measurement. A master reference clock (40) controls the PLL with a stability and accuracy sufficient to measure low frequency wander. Wander data are available from the DSP as an integral of the DDS operating frequency. The DSP also performs the required loop filter function and high pass filters the wander data to provide subband jitter data. This invention digitally controls the PLL filter high pass bandwidth down to very low frequencies to accurately measure low frequency jitter and wander.
摘要翻译：电信号抖动和漂移测量系统（30）实时操作并且数字地控制执行测量的带宽。数字锁相环（“PLL”）（34）包括相位检测器（44），低通滤波器（48,56），模数转换器（“ADC”）（54），数字信号处理器（“DSP”）（32），直接数字合成器（“DDS”）（38）和跟踪振荡器（39）。相位检测器接收与从DDS得到的信号进行比较的输入信号。相位检测器信号包含由ADC滤波和数字化的漂移和抖动数据。 DSP接收数据并执行比例积分控制功能，通过数字控制DDS频率来锁定PLL。 DDS以相位累积寄存器确定的精确速率生成时钟信号。跟踪振荡器锁定到DDS频率的倍数，以增加相位测量的分辨率。主参考时钟（40）以足以测量低频漂移的稳定性和精度来控制PLL。漂移数据可从DSP获得，作为DDS工作频率的一个组成部分。 DSP还执行所需的环路滤波器功能，高通滤波漂移数据以提供子带抖动数据。本发明将PLL滤波器的高通带宽数字控制到非常低的频率，以精确测量低频抖动和漂移。

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