专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5989961A Fabrication method of a vertical channel transistor 失效
标题翻译：垂直沟道晶体管的制造方法
公开(公告)号：US5989961A
公开(公告)日：1999-11-23
申请号：US116904
申请日：1998-07-17
申请人： Jeon Wook Yang , Jae Kyoung Mun , Eung Gie Oh , Jae Jin Lee , Kwang Eui Pyun
发明人： Jeon Wook Yang , Jae Kyoung Mun , Eung Gie Oh , Jae Jin Lee , Kwang Eui Pyun
IPC分类号： H01L29/78 , H01L21/338 , H01L29/812 , H01L21/336
CPC分类号： H01L29/66856 , H01L29/812
摘要： Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.
摘要翻译：公开了用于制造垂直沟道晶体管的方法，包括以下步骤：选择性地将高浓度的掺杂剂注入到半导体衬底中以形成源极区; 首先使用绝缘体和第一光致抗蚀剂图案作为掩模蚀刻半导体衬底; 其次使用具有对应于所述源区域的形状的第二光致抗蚀剂图案作为掩模蚀刻所述基板; 使用所述第二光致抗蚀剂图案作为掩模将低浓度的掺杂剂注入暴露的衬底中以形成垂直沟道层; 使用相同的掩模将高浓度的掺杂剂注入暴露的衬底中以形成漏区; 激活所述掺杂剂，并在所述漏极区上形成欧姆接触层; 第三次使用第三光致抗蚀剂图案进行蚀刻，以将基板的第一蚀刻部分暴露为掩模; 在通过第三次蚀刻暴露的衬底上沉积栅极金属; 并分别接线金属。本发明可以容易地制造具有低寄生电阻和非常小的栅极长度的垂直沟道晶体管，而无需复杂的复杂工艺。

2. 发明授权

US5895930A Infrared photodetector with doping superlattice structure 失效
标题翻译：具有掺杂超晶格结构的红外光电探测器
公开(公告)号：US5895930A
公开(公告)日：1999-04-20
申请号：US891495
申请日：1997-07-11
申请人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park , Kwang-Eui Pyun
发明人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park , Kwang-Eui Pyun
IPC分类号： H01L31/09 , H01L31/0352 , H01L29/06
CPC分类号： B82Y20/00 , H01L31/035236
摘要： This invention provides infrared sensing photodetector and a method therefor which provides a structure for effectively absorbing a light incident in a normal direction on a substrate, and a method compatible with existing processes for making integrated circuitry. An infrared sensing photodetector includes a compound semiconductor substrate of a first conductivity type, superlattice areas having implanted impurity ions of a second conductivity type opposite to the compound semiconductor substrate, each being spaced a predetermined distance each other in a selected region of the semiconductor substrate, a first collector area and a first emitter area which are formed in both end portions positioned perpendicular relative to the doped superlattice areas, a first collector electrode and a first emitter electrode formed on the first collector area and the first emitter area, respectively, a second collector area and a second emitter area which are spaced a predetermined distance in a horizontal direction on the doped superlattice area, and a second collector electrode and a second emitter electrode formed on the second collector area and the second emitter area, respectively.
摘要翻译：本发明提供了一种红外感测光电检测器及其方法，其提供了用于有效吸收在基板上沿正向入射的光的结构，以及与用于制造集成电路的现有工艺兼容的方法。红外感测光电检测器包括具有第一导电类型的化合物半导体衬底，具有注入的与化合物半导体衬底相反的第二导电类型的杂质离子的超晶格区域，在半导体衬底的选定区域中彼此隔开预定距离，第一集电极区域和第一发射极区域，其形成在相对于掺杂的超晶格区域垂直定位的两个端部中，第一集电极电极和第一发射极电极分别形成在第一集电区域和第一发射极区域上，集电极区域和在掺杂超晶格区域上在水平方向上隔开预定距离的第二发射极区域，以及分别形成在第二集电极区域和第二发射极区域上的第二集电极电极和第二发射极电极。

3. 发明授权

US5580803A Production method for ion-implanted MESFET having self-aligned lightly doped drain structure and T-type gate 失效
标题翻译：具有自对准轻掺杂漏极结构和T型栅极的离子注入MESFET的制备方法
公开(公告)号：US5580803A
公开(公告)日：1996-12-03
申请号：US566709
申请日：1995-12-04
申请人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park
发明人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park
IPC分类号： H01L21/28 , H01L21/285 , H01L21/306 , H01L21/336 , H01L21/338 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/78 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/0891 , H01L29/1029 , H01L29/42316 , H01L29/452 , H01L29/66878 , H01L29/8128
摘要： A production method for ion-implanted MESFET having self-aligned LDD structure and T-type gate, that the reverse mesa portion is formed at a predetermined part of the channel region which the source and drain regions are formed at both side by using caps layer, the ion is injected between the source and drain regions and the channel region as the small energy and low concentration by using the reverse mesa as the mask, the source and drain regions of the low concentration is formed so that drain part has more broadly than source part, and the gate electrode and the source and drain regions of the low concentration are not contacted at the formed groove which is removed the surface of the reverse mesa portion or the reverse mesa portion.
摘要翻译：一种具有自对准LDD结构和T型栅极的离子注入MESFET的制造方法，在沟道区的预定部分形成反向台面部分，该栅极和漏极区域通过使用盖层形成在两侧，通过使用反向台面作为掩模，将离子注入到源极和漏极区域和沟道区域之间作为小的能量和低浓度，形成低浓度的源极和漏极区域，使得漏极部分比源极部分，并且低浓度的栅极电极和源极和漏极区域在被去除反向台面部分或反向台面部分的表面的形成的沟槽处不接触。

4. 发明授权

US5856232A Method for fabricating T-shaped electrode and metal layer having low resistance 失效
标题翻译：用于制造具有低电阻的T形电极和金属层的方法
公开(公告)号：US5856232A
公开(公告)日：1999-01-05
申请号：US675972
申请日：1996-07-05
申请人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
发明人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/41 , H01L29/812
CPC分类号： H01L21/28587 , H01L21/28581 , Y10S148/10
摘要： A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.
摘要翻译：一种制造T形栅电极的方法包括以下步骤：在半导体衬底上形成精细栅极图案; 在其上形成有栅极图案的半导体衬底上形成绝缘层，并在绝缘层上形成平坦化层以使半导体衬底的表面平坦化; 蚀刻平坦化层以暴露绝缘层的顶部; 使用平坦化层作为掩模，各向同性蚀刻绝缘层以露出栅极图案; 蚀刻暴露的栅极图案以选择性地暴露半导体衬底; 沉积栅极金属以覆盖暴露的基板，绝缘层和平坦化层，以形成T形门; 同时除去平坦化层，从而形成T形门金属，生产率提高。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式