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1. 发明授权

US5989961A Fabrication method of a vertical channel transistor 失效
标题翻译：垂直沟道晶体管的制造方法
公开(公告)号：US5989961A
公开(公告)日：1999-11-23
申请号：US116904
申请日：1998-07-17
申请人： Jeon Wook Yang , Jae Kyoung Mun , Eung Gie Oh , Jae Jin Lee , Kwang Eui Pyun
发明人： Jeon Wook Yang , Jae Kyoung Mun , Eung Gie Oh , Jae Jin Lee , Kwang Eui Pyun
IPC分类号： H01L29/78 , H01L21/338 , H01L29/812 , H01L21/336
CPC分类号： H01L29/66856 , H01L29/812
摘要： Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.
摘要翻译：公开了用于制造垂直沟道晶体管的方法，包括以下步骤：选择性地将高浓度的掺杂剂注入到半导体衬底中以形成源极区; 首先使用绝缘体和第一光致抗蚀剂图案作为掩模蚀刻半导体衬底; 其次使用具有对应于所述源区域的形状的第二光致抗蚀剂图案作为掩模蚀刻所述基板; 使用所述第二光致抗蚀剂图案作为掩模将低浓度的掺杂剂注入暴露的衬底中以形成垂直沟道层; 使用相同的掩模将高浓度的掺杂剂注入暴露的衬底中以形成漏区; 激活所述掺杂剂，并在所述漏极区上形成欧姆接触层; 第三次使用第三光致抗蚀剂图案进行蚀刻，以将基板的第一蚀刻部分暴露为掩模; 在通过第三次蚀刻暴露的衬底上沉积栅极金属; 并分别接线金属。本发明可以容易地制造具有低寄生电阻和非常小的栅极长度的垂直沟道晶体管，而无需复杂的复杂工艺。

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