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1. 发明授权

US08866122B1 Resistive switching devices having a buffer layer and methods of formation thereof 有权
标题翻译：具有缓冲层的电阻式开关器件及其形成方法
公开(公告)号：US08866122B1
公开(公告)日：2014-10-21
申请号：US13517653
申请日：2012-06-14
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.
摘要翻译：在一个实施例中，电阻式开关器件包括底部电极，开关层，缓冲层和顶部电极。开关层设置在底部电极上。缓冲层设置在开关层上并提供存储金属离子的缓冲液。缓冲层包括记忆金属与含有锑，锡，铋，铝，锗，硅或砷的合金元素的合金。顶部电极设置在缓冲层上方并提供存储金属的源。

2. 发明授权

US08847192B2 Resistive switching devices having alloyed electrodes and methods of formation thereof 有权
标题翻译：具有合金电极的电阻式开关器件及其形成方法
公开(公告)号：US08847192B2
公开(公告)日：2014-09-30
申请号：US13558296
申请日：2012-07-25
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
IPC分类号： H01L47/00 , H01L45/00
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.
摘要翻译：根据本发明的实施例，电阻式开关装置包括底电极，设置在底电极上的开关层和设置在开关层上的顶电极。顶部电极包括记忆金属和合金元素的合金。顶部电极提供存储金属的源。存储器金属被配置为改变开关层的状态。

3. 发明申请

US20130062587A1 Resistive Switching Devices Having Alloyed Electrodes And Methods of Formation Thereof 有权
标题翻译：具有合金电极的电阻式开关器件及其形成方法
公开(公告)号：US20130062587A1
公开(公告)日：2013-03-14
申请号：US13558296
申请日：2012-07-25
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.
摘要翻译：根据本发明的实施例，电阻式开关装置包括底电极，设置在底电极上的开关层和设置在开关层上的顶电极。顶部电极包括记忆金属和合金元素的合金。顶部电极提供存储金属的源。存储器金属被配置为改变开关层的状态。

4. 发明授权

US08426839B1 Conducting bridge random access memory (CBRAM) device structures 有权
标题翻译：传导桥随机存取存储器（CBRAM）器件结构
公开(公告)号：US08426839B1
公开(公告)日：2013-04-23
申请号：US12767552
申请日：2010-04-26
申请人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
发明人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
IPC分类号： H01L45/00 , H01L29/04 , H01L29/12
CPC分类号： H01L45/085 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/1608 , H01L45/165 , H01L45/1658 , H01L45/1675 , H01L45/1683
摘要： A conductive bridging memory cell may include an ion conductor layer formed over an active electrode that is a source of conductive ions for the ion conductor; a conductive layer; and a barrier layer formed below the active layer and in contact with the conductive, the barrier layer substantially preventing a movement of conductive ions therethrough.
摘要翻译：导电桥接存储单元可以包括在作为离子导体的导电离子源的有源电极上形成的离子导体层; 导电层; 以及形成在有源层下方并与导体接触的阻挡层，阻挡层基本上防止导电离子通过其移动。

5. 发明授权

US09401472B1 Programmable impedance elements and devices that include such elements 有权
标题翻译：可编程阻抗元件和包含这些元件的器件
公开(公告)号：US09401472B1
公开(公告)日：2016-07-26
申请号：US13242391
申请日：2011-09-23
申请人： Chakravarthy Gopalan , Antonio R. Gallo , Yi Ma
发明人： Chakravarthy Gopalan , Antonio R. Gallo , Yi Ma
IPC分类号： H01L45/00 , H01L29/41 , G11C13/00
CPC分类号： H01L45/00 , G11C13/0009 , G11C13/0011 , H01L45/085 , H01L45/1266 , H01L45/1675 , H01L45/1683
摘要： Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.
摘要翻译：公开了可编程阻抗元件的结构，装置和方法。方法可以包括：在延伸穿过盖层的电极开口内形成第一电极层; 平坦化以暴露盖层的顶部; 清洁盖层的暴露的顶表面以从先前的工艺步骤中除去残留的物质。附加方法可以包括至少形成其中形成有活性金属的基离子导体层，其可以在离子导体层内离子传导; 以及形成抑制剂材料，其与单独的活性金属相比，减轻了基础离子导体层内的活性金属的聚集。可编程阻抗元件和/或器件可以具有平行于形成在单元电介质中的单元开口的底部和侧面的开关材料和电极。其他实施例可以包括具有活性金属或与活性电极接触的两个离子导体层的合金的离子导体层。

6. 发明授权

US08829482B1 Variable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same 有权
标题翻译：可变阻抗存储器件结构和制造方法包括可编程阻抗存储单元及其形成方法
公开(公告)号：US08829482B1
公开(公告)日：2014-09-09
申请号：US13242854
申请日：2011-09-23
申请人： Antonio R. Gallo , Chakravarthy Gopalan , Yi Ma
发明人： Antonio R. Gallo , Chakravarthy Gopalan , Yi Ma
IPC分类号： H01L29/778
CPC分类号： H01L45/145 , G11C13/0011 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142
摘要： A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.
摘要翻译：可编程阻抗存储器件结构可以包括形成在第一阻挡层的平坦表面上的多层可变阻抗存储元件，所述多层可变阻抗存储元件包括基本上平行于平面的多个层，包括存储器材料层与平坦表面接触，第一阻挡层形成在第一绝缘层之上; 以及形成在所述存储元件上方的第二阻挡层，其具有与所述平坦表面基本平行的顶表面。第一和第二阻挡层对于存储材料层内的至少一个元件可以具有比第一绝缘层更低的迁移率，并且存储材料层可以通过在至少两个不同的阻抗状态之间施加电场来编程。

7. 发明授权

US07402847B2 Programmable logic circuit and method of using same 有权
标题翻译：可编程逻辑电路及其使用方法
公开(公告)号：US07402847B2
公开(公告)日：2008-07-22
申请号：US11404160
申请日：2006-04-13
申请人： Michael N Kozicki , Maria Mitkova , Chakravarthy Gopalan , Muralikrishnan Balakrishnan
发明人： Michael N Kozicki , Maria Mitkova , Chakravarthy Gopalan , Muralikrishnan Balakrishnan
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/101 , H01L27/118 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic cell, and a programmable memory element located at the intersection of two wires. The programmable element acts as a switch and as memory for the logic circuit.
摘要翻译：公开了一种适用于微处理器应用的可编程逻辑电路，包括可编程存储器元件，以及使用该电路的方法。可编程电路包括至少一个逻辑单元，耦合到逻辑单元的线和列的行以及位于两条线的交叉处的可编程存储元件。可编程元件充当开关和作为逻辑电路的存储器。

8. 发明授权

US08816314B2 Contact structure and method for variable impedance memory element 有权
标题翻译：可变阻抗存储元件的接触结构和方法
公开(公告)号：US08816314B2
公开(公告)日：2014-08-26
申请号：US13470286
申请日：2012-05-12
申请人： Chakravarthy Gopalan
发明人： Chakravarthy Gopalan
IPC分类号： H01L29/02
CPC分类号： H01L45/1266 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/16
摘要： A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.
摘要翻译：存储元件可以包括形成在形成在蚀刻停止层上的至少一个绝缘层中的开口，其暴露出开口底部的第一电极部分和蚀刻停止层; 第二电极部分，形成在所述开口的至少一个侧表面上并与所述第一电极部分接触，所述第二电极部分不填充所述开口并且基本上不形成在所述至少一个绝缘层的顶表面上; 以及形成在所述至少一个绝缘层的顶表面上并与所述第二电极部分接触的至少一个存储层，所述至少一个存储层可在至少两个阻抗状态之间可逆地编程。还公开了形成这种存储元件的方法。

9. 发明授权

US07101728B2 Programmable structure including an oxide electrolyte and method of forming programmable structure 有权
标题翻译：可编程结构包括氧化物电解质和形成可编程结构的方法
公开(公告)号：US07101728B2
公开(公告)日：2006-09-05
申请号：US10796808
申请日：2004-03-08
申请人： Michael N. Kozicki , Maria Mitkova , Chakravarthy Gopalan , Muralikrish Balakrishnan
发明人： Michael N. Kozicki , Maria Mitkova , Chakravarthy Gopalan , Muralikrish Balakrishnan
IPC分类号： H01L21/00 , H00L29/10
CPC分类号： G11C11/34 , B82Y10/00 , G11C11/5614 , G11C13/0011 , G11C13/04 , G11C23/00 , G11C2013/0047 , G11C2207/104 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1658 , H01L45/1675 , H01L45/1683
摘要： A microelectronic programmable structure suitable for storing information and methods of forming and programming the structure are disclosed. The programmable structure generally includes an oxide ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.
摘要翻译：公开了一种适用于存储信息的微电子可编程结构和形成和编程结构的方法。可编程结构通常包括氧化物离子导体和多个电极。可以通过向结构施加能量来改变结构的电特性，因此可以使用该结构存储信息。

10. 发明申请

US20090067213A1 Method of forming controllably conductive oxide 有权
标题翻译：形成可控导电氧化物的方法
公开(公告)号：US20090067213A1
公开(公告)日：2009-03-12
申请号：US11899597
申请日：2007-09-06
申请人： Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
发明人： Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
IPC分类号： G11C11/00 , B05D5/12
CPC分类号： H01L45/165 , H01L21/31683 , H01L45/04 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1633
摘要： In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.
摘要翻译：在制造存储器件时，提供第一电极。在其上形成合金，并且将该合金氧化以提供氧化物层。第二电极设置在氧化物层上。在制造存储器件的另一方法中，提供第一电极。在第一电极上提供氧化物，以及注入步骤，用于在氧化物中植入材料以形成包含氧缺陷和/或缺陷的氧化物和/或缺陷的层。然后在该层上形成第二电极。

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