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1. 发明申请

US20170084624A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH VERTICAL AND HORIZONTAL CHANNELS IN STACK STRUCTURE HAVING ELECTRODES VERTICALLY STACKED ON THE SUBSTRATE 有权
公开(公告)号：US20170084624A1
公开(公告)日：2017-03-23
申请号：US15245218
申请日：2016-08-24
申请人： CHANGHYUN LEE , HEONKYU LEE , SHINHWAN KANG , YOUNGWOO PARK
发明人： CHANGHYUN LEE , HEONKYU LEE , SHINHWAN KANG , YOUNGWOO PARK
IPC分类号： H01L27/115 , H01L23/535
CPC分类号： H01L27/11582 , H01L23/5283 , H01L23/535 , H01L27/11524 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11573
摘要： A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

2. 发明授权

US09224493B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US09224493B2
公开(公告)日：2015-12-29
申请号：US14280920
申请日：2014-05-19
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/26 , G11C16/30 , G11C16/34 , G11C8/10 , G11C11/56 , G11C16/04 , G11C29/00
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

3. 发明申请

US20150340093A1 NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US20150340093A1
公开(公告)日：2015-11-26
申请号：US14819428
申请日：2015-08-06
申请人： Changhyun LEE
发明人： Changhyun LEE
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
摘要翻译：根据示例性实施例，非易失性存储器件包括具有多个串联连接的选择晶体管和与串联连接的选择晶体管的一端串联连接的多个存储单元的多个串。控制逻辑被配置为执行用于设置串联连接的选择晶体管中的至少一个的阈值电压的编程操作。

4. 发明授权

US08829589B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08829589B2
公开(公告)日：2014-09-09
申请号：US13757273
申请日：2013-02-01
申请人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
发明人： Changhyun Lee , Byoungkeun Son , Youngwoo Park
IPC分类号： H01L29/788 , H01L29/04 , H01L29/792
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/04 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.
摘要翻译：三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。分离图案可以包括至少一个分离半导体层。

5. 发明申请

US20140198572A1 STRING SELECTION STRUCTURE OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 有权
标题翻译：三维半导体器件的STRING选择结构
公开(公告)号：US20140198572A1
公开(公告)日：2014-07-17
申请号：US14088127
申请日：2013-11-22
申请人： CHANGHYUN LEE , SUNG-MIN HWANG
发明人： CHANGHYUN LEE , SUNG-MIN HWANG
IPC分类号： H01L23/50 , G11C16/08
CPC分类号： H01L23/50 , G11C11/5635 , G11C16/0483 , G11C16/08 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.
摘要翻译：三维半导体器件包括彼此堆叠的第一和第二选择线。水平地横越第一和第二选择线的上线。第一和第二垂直图案垂直地跨越第一和第二选择线。第一和第二垂直图案共同连接到上线。第一和第二垂直图案中的每一个构成彼此串联连接的第一和第二选择晶体管。第一和第二垂直图案的第一选择晶体管分别由第一和第二选择线控制。

6. 发明申请

US20140029344A1 NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US20140029344A1
公开(公告)日：2014-01-30
申请号：US14043256
申请日：2013-10-01
申请人： Changhyun LEE , Jinman HAN , Doogon KIM , Sunghoi HUR , Jongin YUN
发明人： Changhyun LEE , Jinman HAN , Doogon KIM , Sunghoi HUR , Jongin YUN
IPC分类号： G11C16/10
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.
摘要翻译：提供了一种非易失性存储器件的编程方法。非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

7. 发明授权

US08581321B2 Nonvolatile memory device and method of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US08581321B2
公开(公告)日：2013-11-12
申请号：US13281612
申请日：2011-10-26
申请人： Byoungkeun Son , Changhyun Lee , Jaegoo Lee , Kwang Soo Seol , Byungkwan You
发明人： Byoungkeun Son , Changhyun Lee , Jaegoo Lee , Kwang Soo Seol , Byungkwan You
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.
摘要翻译：非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

8. 发明申请

US20120138394A1 CONTROL METHOD FOR PARKING RELEASE APPARATUS OF SHIFT-BY-WIRE SHIFTING DEVICE 有权
标题翻译：通过换线装置停放释放装置的控制方法
公开(公告)号：US20120138394A1
公开(公告)日：2012-06-07
申请号：US13285539
申请日：2011-10-31
申请人： Hangil PARK , Changhyun Lee
发明人： Hangil PARK , Changhyun Lee
IPC分类号： B60T13/74 , F16D66/00
CPC分类号： B60T7/12 , B60T13/746 , Y10T477/6437 , Y10T477/644 , Y10T477/853
摘要： A control method for a parking release apparatus of a shift-by-wire shifting device can improve the commercial value of a vehicle by improving safety of the vehicle and preventing robbery, by interfering with or preventing an attempt of abnormally and manually releasing a parking state of the vehicle when there is no problem in the electric system of the vehicle, using a part provided to be manually operated in the parking release apparatus such that a P-stage state and an N-stage state can be manually switched when a problem, such as discharge, occurs in the electric system, in the vehicle equipped with a shift by wire apparatus.
摘要翻译：线移线装置的停车解除装置的控制方法可以通过提高车辆的安全性和防止抢劫，通过干扰或防止异常地和手动地解除停车状态的尝试来提高车辆的商业价值在车辆的电气系统中没有问题的情况下，使用在停车解除装置中手动操作的部件，使得当出现问题时可以手动切换P级状态和N级状态，例如放电，发生在电气系统中，在配备有有线装置的换档的车辆中。

9. 发明申请

US20120081958A1 NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20120081958A1
公开(公告)日：2012-04-05
申请号：US13243968
申请日：2011-09-23
申请人： CHANGHYUN LEE , Byoungkeun Son
发明人： CHANGHYUN LEE , Byoungkeun Son
IPC分类号： G11C16/04
CPC分类号： H01L27/11582 , G11C16/0408 , G11C16/0483 , H01L21/28008 , H01L23/50 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L2924/00 , H01L2924/0002
摘要： Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.
摘要翻译：提供了非易失性存储器件及其形成方法。非易失性存储器件包括多个字线，接地选择线，串选择线和虚拟字线。虚拟字线和接地选择线之间以及虚拟字线和字线之间的距离中的每一个都大于彼此相邻的一对字线之间的距离。

10. 发明授权

US08064259B2 Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers 失效
标题翻译：包括连接到绝缘层的电荷存储层的非易失性NAND型存储器件
公开(公告)号：US08064259B2
公开(公告)日：2011-11-22
申请号：US12617972
申请日：2009-11-13
申请人： Changhyun Lee , Jungdal Choi , Yoocheol Shin , Yongsik Yim
发明人： Changhyun Lee , Jungdal Choi , Yoocheol Shin , Yongsik Yim
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.
摘要翻译：非易失性存储器件包括一个包括多个中间字线的字线组和在衬底上具有电荷存储图案的边缘字线。外围线设置在字线组的一侧，使得边缘字线在周边字线和中间字线之间。外围线包括绝缘层和栅电极。中间和边缘字线的电荷存储模式彼此分离，并且边缘字线的电荷存储模式在一侧延伸以连接到外围线的绝缘层。还公开了形成非易失性存储器件的方法。

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