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1. 发明授权

US08278170B2 Methods of forming nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：形成其中具有垂直集成的非易失性存储单元子串的非易失性存储器件的方法
公开(公告)号：US08278170B2
公开(公告)日：2012-10-02
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/336
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

2. 发明授权

US08546869B2 Nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：在其中具有垂直集成的非易失性存储单元子串的非易失性存储器件
公开(公告)号：US08546869B2
公开(公告)日：2013-10-01
申请号：US13600829
申请日：2012-08-31
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/8239
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

3. 发明申请

US20120327715A1 NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN 有权
标题翻译：具有垂直集成非易失性存储单元子带的非易失性存储器件
公开(公告)号：US20120327715A1
公开(公告)日：2012-12-27
申请号：US13600829
申请日：2012-08-31
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

4. 发明申请

US20140016408A1 NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN 有权
标题翻译：具有垂直集成非易失性存储单元子带的非易失性存储器件
公开(公告)号：US20140016408A1
公开(公告)日：2014-01-16
申请号：US14024844
申请日：2013-09-12
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：根据本发明的实施例的非易失性存储器件包括高度集成的非易失性存储器单元的垂直堆叠。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

5. 发明申请

US20120003800A1 Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby 有权
标题翻译：形成具有垂直集成的非易失性存储器单元子串的非易失性存储器件的方法及其形成的非易失性存储器件
公开(公告)号：US20120003800A1
公开(公告)日：2012-01-05
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/8239
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

6. 发明授权

US08570805B2 Nonvolatile memory device, programming method thereof and memory system including the same 有权
公开(公告)号：US08570805B2
公开(公告)日：2013-10-29
申请号：US13029518
申请日：2011-02-17
申请人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
发明人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
IPC分类号： G11C16/04
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

7. 发明申请

US20110199829A1 Nonvolatile Memory Device, Programming Method Thereof And Memory System Including The Same 有权
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US20110199829A1
公开(公告)日：2011-08-18
申请号：US13029518
申请日：2011-02-17
申请人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
发明人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.
摘要翻译：提供了一种非易失性存储器件的编程方法。非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

8. 发明授权

US08929145B2 Nonvolatile memory device, programming method thereof and memory system including the same 有权
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US08929145B2
公开(公告)日：2015-01-06
申请号：US14043256
申请日：2013-10-01
申请人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
发明人： Changhyun Lee , Jinman Han , Doogon Kim , Sunghoi Hur , Jongin Yun
IPC分类号： G11C16/04 , H01L27/115 , G11C16/10 , H01L29/792
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.
摘要翻译：提供了一种非易失性存储器件的编程方法。非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

9. 发明授权

US08644064B2 Memory semiconductor device and method of operating the same 有权
标题翻译：存储器半导体器件及其操作方法
公开(公告)号：US08644064B2
公开(公告)日：2014-02-04
申请号：US13107206
申请日：2011-05-13
申请人： Byungkyu Cho , Changhyun Lee , Sunghoi Hur
发明人： Byungkyu Cho , Changhyun Lee , Sunghoi Hur
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/26
摘要： In a read step or a program (write) verification step of a semiconductor memory device, read voltages different from one another are applied to a pair of word lines respectively disposed on both sides of a selected word line to suppress the enlargement of program distribution.
摘要翻译：在半导体存储器件的读取步骤或程序（写入）验证步骤中，彼此不同的读取电压被施加到分别设置在所选字线的两侧上的一对字线，以抑制程序分配的扩大。

10. 发明授权

US09947686B2 Semiconductor device including a stack having a sidewall with recessed and protruding portions 有权
公开(公告)号：US09947686B2
公开(公告)日：2018-04-17
申请号：US15456841
申请日：2017-03-13
申请人： Byoungkeun Son , Yoocheol Shin , Changhyun Lee , Hyunjung Kim , Chung-Il Hyun
发明人： Byoungkeun Son , Yoocheol Shin , Changhyun Lee , Hyunjung Kim , Chung-Il Hyun
IPC分类号： H01L29/788 , H01L27/11582 , H01L27/11565 , H01L21/28 , H01L27/1157
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

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