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    • 1. 发明申请
    • REGULATOR CIRCUIT WITH ENHANCED RIPPLE REDUCTION SPEED
    • 具有增强纹波降低速度的调节器电路
    • US20170063217A1
    • 2017-03-02
    • US14840257
    • 2015-08-31
    • SEUNG CHUL SHINHYUNG JONG KOJUNG SU KIMYONG IN PARKWON HYUK JUNGYUN CHEOL HAN
    • SEUNG CHUL SHINHYUNG JONG KOJUNG SU KIMYONG IN PARKWON HYUK JUNGYUN CHEOL HAN
    • H02M1/14G05F1/575
    • G05F1/575H02M1/14H02M2001/0003H02M2001/0025
    • A regulator circuit includes an OP-amp, buffer, power transistor, voltage divider, load, and feedback current generator. The OP-amp generates first voltage signal by amplifying a difference between an input voltage signal and a feedback voltage signal. The OP-amp drives a first node as the first voltage signal. The buffer drives a second node as a second voltage signal generated based on the first voltage signal. The power transistor includes a drain terminal receiving a supply voltage, a gate terminal connected to the second node, and a source terminal connected to a third node. The voltage divider generates the feedback voltage signal by dividing an output voltage signal of the third node. The load includes a terminal connected to the third node and another terminal receiving a ground voltage. The feedback current generator provides a first feedback current corresponding to a ripple of the output voltage signal to the first node for enhancing a speed at which the ripple reduced.
    • 调节器电路包括OP放大器,缓冲器,功率晶体管,分压器,负载和反馈电流发生器。 OP放大器通过放大输入电压信号和反馈电压信号之间的差异来产生第一电压信号。 OP-amp驱动第一个节点作为第一个电压信号。 缓冲器驱动第二节点作为基于第一电压信号产生的第二电压信号。 功率晶体管包括接收电源电压的漏极端子,连接到第二节点的栅极端子和连接到第三节点的源极端子。 分压器通过分压第三节点的输出电压信号来产生反馈电压信号。 负载包括连接到第三节点的终端和接收地电压的另一终端。 反馈电流发生器提供对应于第一节点的输出电压信号的纹波的第一反馈电流,以增加纹波减小的速度。
    • 3. 发明授权
    • Equalizers and methods for equalizing
    • 均衡和均衡的方法
    • US07733950B2
    • 2010-06-08
    • US11318852
    • 2005-12-28
    • Hyung-Jong Ko
    • Hyung-Jong Ko
    • H03H7/30
    • H04B3/145G11B20/10009G11B20/10046H03H11/0444H03H11/0472H03H11/08
    • Equalizers and methods of equalizing, wherein an equalizer may include includes n (where n is an integer ≧) biquad circuits each include an input node, a biquad band pass node and a biquad low pass node, a first summing circuit summing an output of the biquad band pass node of the nth biquad circuit and an output of the biquad low pass node of the nth biquad circuit, a second summing circuit subtracting the output of the biquad low pass node of the (n−1)th biquad circuit from the output of the first summing circuit and amplifying the summed result by a constant, and a third summing circuit summing an output of the second summing circuit and the output of the biquad low pass node of the nth biquad circuit, wherein the n biquad circuits are Gm-C biquad circuits each having transconductors connected in a self-feedback configuration to the biquad band pass node of the corresponding n biquad circuit. The equalizer may increase a filter bandwidth and/or maintain a specific boosting gain while reducing circuit size.
    • 均衡器和均衡方法,其中均衡器可以包括n(其中n是整数≥)二进制电路各自包括输入节点,双二进制带通节点和双二阶低通节点,第一求和电路将 第n个二进制电路的双二进制带通节点和第n个二进制电路的二进制低通节点的输出,第二加法电路从输出中减去第(n-1)个二进制电路的二进制低通节点的输出 以及将第二加法电路的输出与第n个二进制电路的二叉低通节点的输出相加的第三求和电路,其中n个二进制电路是Gm- 各自具有以自反馈配置连接到相应的n二进制电路的二进制带通节点的跨导体的C二极二极管。 均衡器可以增加滤波器带宽和/或维持特定的升压增益同时减小电路尺寸。
    • 8. 发明申请
    • Equalizers and methods for equalizing
    • 均衡和均衡的方法
    • US20060140263A1
    • 2006-06-29
    • US11318852
    • 2005-12-28
    • Hyung-Jong Ko
    • Hyung-Jong Ko
    • H03K5/159
    • H04B3/145G11B20/10009G11B20/10046H03H11/0444H03H11/0472H03H11/08
    • Equalizers and methods of equalizing, wherein an equalizer may include includes n (where n is an integer ≧) biquad circuits each include an input node, a biquad band pass node and a biquad low pass node, a first summing circuit summing an output of the biquad band pass node of the nth biquad circuit and an output of the biquad low pass node of the nth biquad circuit, a second summing circuit subtracting the output of the biquad low pass node of the (n-1)th biquad circuit from the output of the first summing circuit and amplifying the summed result by a constant, and a third summing circuit summing an output of the second summing circuit and the output of the biquad low pass node of the nth biquad circuit, wherein the n biquad circuits are Gm-C biquad circuits each having transconductors connected in a self-feedback configuration to the biquad band pass node of the corresponding n biquad circuit. The equalizer may increase a filter bandwidth and/or maintain a specific boosting gain while reducing circuit size.
    • 均衡器和均衡方法,其中均衡器可以包括n(其中n是整数> =)二进制电路各自包括输入节点,双二进制带通节点和双二进制低通节点,第一求和电路将 第n个二进制电路的双二进制带通节点和第n个二进制电路的二进制低通节点的输出,第二加法电路从第(n-1)个二进制电路的双二阶低通节点的输出减去第(n-1) 输出第一求和电路,并将求和结果乘以常数;以及第三求和电路,将第二求和电路的输出与第n个二进制电路的双二阶低通节点的输出相加,其中n个二进制电路为Gm -C双二阶电路各自具有以自反馈配置连接到相应的n二进制电路的二进制带通节点的跨导体。 均衡器可以增加滤波器带宽和/或维持特定的升压增益同时减小电路尺寸。