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1. 发明授权

US08058141B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US08058141B2
公开(公告)日：2011-11-15
申请号：US12861111
申请日：2010-08-23
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

2. 发明授权

US07217624B2 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same 失效
公开(公告)号：US07217624B2
公开(公告)日：2007-05-15
申请号：US11024472
申请日：2004-12-30
申请人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
发明人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7887 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L29/66825 , H01L29/788
摘要： The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

3. 发明申请

US20060160286A1 Memory device and method for fabricating the same 有权
公开(公告)号：US20060160286A1
公开(公告)日：2006-07-20
申请号：US11385217
申请日：2006-03-20
申请人： Eung-Rim Hwang , Se-Aug Jang , Tae-Woo Jung , Seo-Min Kim , Woo-Jin Kim , Hyung-Soon Park , Young-Bog Kim , Hong-Seon Yang , Hyun-Chul Sohn
发明人： Eung-Rim Hwang , Se-Aug Jang , Tae-Woo Jung , Seo-Min Kim , Woo-Jin Kim , Hyung-Soon Park , Young-Bog Kim , Hong-Seon Yang , Hyun-Chul Sohn
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/10855 , H01L27/10888 , H01L27/115 , H01L29/7886
摘要： Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

4. 发明申请

US20060094199A1 Method for forming capacitor of semiconductor device 失效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US20060094199A1
公开(公告)日：2006-05-04
申请号：US11122597
申请日：2005-05-05
申请人： Deok Sin Kil , Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
发明人： Deok Sin Kil , Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/45531 , C23C16/56 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L28/40
摘要： Disclosed is a method for forming a capacitor of a semiconductor device, which can improve a leakage current characteristic in applying HfxAlyOz as a dielectric film. In such a method, HfxAlyOz thin films are deposited on a storage electrode to form an HfxAlyOz dielectric film and a plate electrode is formed on the dielectric film. The HfxAlyOz dielectric film consists of laminated HfxAlyOz thin films which are different in compositions of Hf and Al such that the lower HfxAlyOz thin film adjoining the storage electrode has a larger composition ratio of Al than that of Hf and the upper HfxAlyOz thin film has a larger composition ratio of Hf than that of Al, and the upper HfxAlyOz thin film is subjected to heat treatment under an oxygen atmosphere after its deposition.
摘要翻译：公开了一种用于形成半导体器件的电容器的方法，其可以改善施加Hf x Al y O z作为电介质膜的漏电流特性。在这种方法中，Hf x Al y O z薄膜沉积在存储电极上以形成Hf x Al y O z电介质膜，并且在电介质膜上形成平板电极。 Hf x Al y O z电介质膜由Hf和Al组成不同的层叠Hf x Al y O z薄膜组成，使得邻近存储电极的下部Hf x Al y O z薄膜具有比Hf组成更高的Al的组成比，并且上部Hf x Al y O z薄膜具有较大的 Hf的组成比高于Al，上层Hf x Al y O z薄膜在沉积后在氧气氛下进行热处理。

5. 发明申请

US20060073666A1 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same 失效
标题翻译：具有导电侧壁间隔物的非易失性存储器件及其制造方法
公开(公告)号：US20060073666A1
公开(公告)日：2006-04-06
申请号：US11024472
申请日：2004-12-30
申请人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
发明人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L29/66825 , H01L29/788
摘要： The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
摘要翻译：本发明涉及具有导电侧壁间隔物的非易失性存储器件及其制造方法。非易失性存储器件包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在栅极绝缘层上的栅极结构; 形成在所述栅极结构的侧壁上的一对侧壁间隔物; 一对导电侧壁间隔物，用于捕获/去除在一对侧壁间隔物上形成的电荷; 形成在所述衬底中的一对轻掺杂漏极区，所述衬底设置在所述栅极结构的侧壁下方; 以及形成在所述基板中的一对源极/漏极区域，所述基极设置在所述一对导电侧壁间隔物的边缘部分的下方。

6. 发明申请

US20060022249A1 Memory device and method for fabricating the same 有权
公开(公告)号：US20060022249A1
公开(公告)日：2006-02-02
申请号：US11053704
申请日：2005-02-07
申请人： Se-Aug Jang , Tae-Woo Jung , Seo-Min Kim , Woo-Jin Kim , Hyung-Soon Park , Young-Bog Kim , Hong-Seon Yang , Hyun-Chul Sohn , Eung-Rim Hwang
发明人： Se-Aug Jang , Tae-Woo Jung , Seo-Min Kim , Woo-Jin Kim , Hyung-Soon Park , Young-Bog Kim , Hong-Seon Yang , Hyun-Chul Sohn , Eung-Rim Hwang
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/11521 , H01L27/10855 , H01L27/10888 , H01L27/115 , H01L29/7886
摘要： Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

7. 发明授权

US06936529B2 Method for fabricating gate-electrode of semiconductor device with use of hard mask 失效
标题翻译：使用硬掩模制造半导体器件栅电极的方法
公开(公告)号：US06936529B2
公开(公告)日：2005-08-30
申请号：US10725320
申请日：2003-12-02
申请人： Kwan-Yong Lim , Heung-Jae Cho , Jung-Ho Lee , Se-Aug Jang , Yong-Soo Kim , Byung-Seop Hong , Jae-Geun Oh , Hong-Seon Yang , Hyun-Chul Sohn
发明人： Kwan-Yong Lim , Heung-Jae Cho , Jung-Ho Lee , Se-Aug Jang , Yong-Soo Kim , Byung-Seop Hong , Jae-Geun Oh , Hong-Seon Yang , Hyun-Chul Sohn
IPC分类号： H01L21/336 , H01L21/28 , H01L21/3205 , H01L21/44 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/2807 , H01L29/4941
摘要： The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.
摘要翻译：本发明涉及一种制造半导体器件的栅电极的方法，所述半导体器件具有能够防止包含在栅极电极中的金属层的异常氧化并抑制应力产生的双重硬掩模。该方法包括以下步骤：在衬底上形成栅极绝缘层; 在所述栅极绝缘层上形成至少含有金属层的栅极层结构; 在低于金属层的氧化温度的温度下在栅极层结构上形成硬掩模氧化物层; 在硬掩模氧化物层上形成硬掩模氮化物层; 将硬掩模氧化物层和硬掩模氮化物层图案化为用于形成栅电极的双重硬掩模; 以及通过使用双重硬掩模作为蚀刻掩模蚀刻栅极层结构来形成栅电极。

8. 发明申请

US20050136593A1 Method for fabricating semiconductor device with dual gate dielectric structure 失效
标题翻译：制造具有双栅电介质结构的半导体器件的方法
公开(公告)号：US20050136593A1
公开(公告)日：2005-06-23
申请号：US10878346
申请日：2004-06-29
申请人： Se-Aug Jang , Heung-Jae Cho , Kwan-Yong Lim , Hyo-Geun Yoon , Seok-Kiu Lee , Hyun-Chul Sohn
发明人： Se-Aug Jang , Heung-Jae Cho , Kwan-Yong Lim , Hyo-Geun Yoon , Seok-Kiu Lee , Hyun-Chul Sohn
IPC分类号： H01L21/31 , H01L21/336 , H01L21/8239 , H01L21/8242 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/11573
摘要： Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.
摘要翻译：公开了一种用于制造具有双栅介质结构的半导体器件的方法。该方法包括以下步骤：在设置有用于NVDRAM的单元区域和用于逻辑电路的外围电路区域的衬底上顺序地形成第一氧化物层，氮化物层和第二氧化物层; 在细胞区域上形成掩模; 通过使用掩模作为蚀刻阻挡层去除形成在外围电路区域中的第二氧化物层来执行第一湿蚀刻工艺; 通过使用剩余在所述单元区域中的所述第二氧化物层作为蚀刻阻挡层来去除形成在所述外围电路区域中的所述氮化物层的第二湿蚀刻工艺; 在保留在外围电路区域中的第一氧化物层上形成第三氧化物层; 以及在所述第二氧化物层和所述第三氧化物层上形成栅电极。

9. 发明申请

US20110165761A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED BY THE SAME 有权
标题翻译：制造半导体器件的方法及其制造的半导体器件
公开(公告)号：US20110165761A1
公开(公告)日：2011-07-07
申请号：US12961054
申请日：2010-12-06
申请人： Myung-Jong KIM , In-Seok Yeo , Dae-Hong Ko , Hyun-Chul Sohn , Mann-Ho Cho , Sang-Yeon Kim
发明人： Myung-Jong KIM , In-Seok Yeo , Dae-Hong Ko , Hyun-Chul Sohn , Mann-Ho Cho , Sang-Yeon Kim
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L21/0237 , B82Y10/00 , B82Y40/00 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02653 , H01L29/0665 , H01L29/0676 , H01L29/66825 , H01L29/7881
摘要： Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
摘要翻译：示例性方法和示例实施例包括制造由其制造的半导体器件和半导体器件的方法。示例性制造方法包括形成第一纳米线，氧化第一纳米线以形成包括第一绝缘体和第二纳米线的第一纳米结构，以及氧化第二纳米线以形成包括第二绝缘体和纳米点的第二纳米结构。示例性半导体器件包括在存储器件中提供存储节点的纳米结构和纳米结构。

10. 发明授权

US07667253B2 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same 失效
标题翻译：具有导电侧壁间隔物的非易失性存储器件及其制造方法
公开(公告)号：US07667253B2
公开(公告)日：2010-02-23
申请号：US11790957
申请日：2007-04-30
申请人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
发明人： Kwan-Yong Lim , Heung-Jae Cho , Yong-Soo Kim , Se-Aug Jang , Hyun-Chul Sohn
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/7887 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L29/66825 , H01L29/788
摘要： The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
摘要翻译：本发明涉及具有导电侧壁间隔物的非易失性存储器件及其制造方法。非易失性存储器件包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在栅极绝缘层上的栅极结构; 形成在所述栅极结构的侧壁上的一对侧壁间隔物; 一对导电侧壁间隔物，用于捕获/去除在一对侧壁间隔物上形成的电荷; 形成在所述衬底中的一对轻掺杂漏极区，所述衬底设置在所述栅极结构的侧壁下方; 以及形成在所述基板中的一对源极/漏极区域，所述基极设置在所述一对导电侧壁间隔物的边缘部分的下方。

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