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1. 发明申请

US20060273381A1 Transistor and method for fabricating the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20060273381A1
公开(公告)日：2006-12-07
申请号：US11157999
申请日：2005-06-21
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

2. 发明授权

US07804129B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US07804129B2
公开(公告)日：2010-09-28
申请号：US11157999
申请日：2005-06-21
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L29/76 , H01L21/3205
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

3. 发明授权

US08058141B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US08058141B2
公开(公告)日：2011-11-15
申请号：US12861111
申请日：2010-08-23
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

4. 发明授权

US07601583B2 Transistor structure of memory device and method for fabricating the same 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US07601583B2
公开(公告)日：2009-10-13
申请号：US11962100
申请日：2007-12-21
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Rohh , Hyun Chul Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Rohh , Hyun Chul Sohn
IPC分类号： H01L29/72
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

5. 发明申请

US20080096355A1 TRANSISTOR STRUCTURE OF MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US20080096355A1
公开(公告)日：2008-04-24
申请号：US11962100
申请日：2007-12-21
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

6. 发明申请

US20070148943A1 Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070148943A1
公开(公告)日：2007-06-28
申请号：US11512572
申请日：2006-08-30
申请人： Soo Hyun Kim , Kwan Yong Lim , Baek Mann Kim , Young Jin Lee , Noh Jung Kwak , Hyun Chul Sohn
发明人： Soo Hyun Kim , Kwan Yong Lim , Baek Mann Kim , Young Jin Lee , Noh Jung Kwak , Hyun Chul Sohn
IPC分类号： H01L21/44
CPC分类号： H01L21/76841 , H01L21/28562 , H01L27/10873 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a WSixNy film or a WSix film by using an ALD process.
摘要翻译：公开了半导体器件的制造方法。该方法包括形成介于硅膜和金属膜之间的扩散阻挡膜的步骤，其功能是防止硅和金属膜之间的扩散。通过使用ALD工艺，由WSixNy膜或WSix膜形成扩散阻挡膜。

7. 发明授权

US07655534B2 Method of forming fin transistor 失效
标题翻译：形成鳍式晶体管的方法
公开(公告)号：US07655534B2
公开(公告)日：2010-02-02
申请号：US11594579
申请日：2006-11-08
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyun Chul Sohn
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyun Chul Sohn
IPC分类号： H01L21/762
CPC分类号： H01L21/823437 , H01L29/66795 , H01L29/7851
摘要： A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.
摘要翻译：通过在具有有源区域和场区域的衬底上形成硬掩模层来形成鳍式晶体管。蚀刻硬掩模层以暴露场区域。通过蚀刻暴露的场区形成沟槽。沟槽填充有SOG层。去除硬掩模层以暴露活性区域。在暴露的有源区上形成外延硅层。然后从沟槽的上端部分地蚀刻SOG层，从而填充沟槽的下部。 HDP氧化物层沉积在填充沟槽的蚀刻SOG层上，从而形成由SOG层和HDP氧化物构成的场氧化物层。蚀刻场氧化物层中的HDP氧化物层以露出外延硅层的两个侧表面。然后在其两个侧表面暴露的外延硅层和场氧化物层上形成栅极。

8. 发明授权

US07629221B2 Method for forming capacitor of semiconductor device 失效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07629221B2
公开(公告)日：2009-12-08
申请号：US11173089
申请日：2005-07-01
申请人： Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
发明人： Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/65
摘要： Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.
摘要翻译：公开了一种形成半导体器件的电容器的方法。在这种方法中，在设置有存储节点插塞的绝缘中间层上形成模具绝缘层，并且蚀刻模具绝缘层以形成存储节点插头暴露的孔。接下来，在包括暴露的存储节点插头的孔表面上形成具有插入的WN层的金属存储电极，并且去除模具绝缘层。最后，在金属储存电极上依次形成电介质层和平板电极。

9. 发明申请

US20060094199A1 Method for forming capacitor of semiconductor device 失效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US20060094199A1
公开(公告)日：2006-05-04
申请号：US11122597
申请日：2005-05-05
申请人： Deok Sin Kil , Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
发明人： Deok Sin Kil , Ki Seon Park , Jae Sung Roh , Hyun Chul Sohn
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/45531 , C23C16/56 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L28/40
摘要： Disclosed is a method for forming a capacitor of a semiconductor device, which can improve a leakage current characteristic in applying HfxAlyOz as a dielectric film. In such a method, HfxAlyOz thin films are deposited on a storage electrode to form an HfxAlyOz dielectric film and a plate electrode is formed on the dielectric film. The HfxAlyOz dielectric film consists of laminated HfxAlyOz thin films which are different in compositions of Hf and Al such that the lower HfxAlyOz thin film adjoining the storage electrode has a larger composition ratio of Al than that of Hf and the upper HfxAlyOz thin film has a larger composition ratio of Hf than that of Al, and the upper HfxAlyOz thin film is subjected to heat treatment under an oxygen atmosphere after its deposition.
摘要翻译：公开了一种用于形成半导体器件的电容器的方法，其可以改善施加Hf x Al y O z作为电介质膜的漏电流特性。在这种方法中，Hf x Al y O z薄膜沉积在存储电极上以形成Hf x Al y O z电介质膜，并且在电介质膜上形成平板电极。 Hf x Al y O z电介质膜由Hf和Al组成不同的层叠Hf x Al y O z薄膜组成，使得邻近存储电极的下部Hf x Al y O z薄膜具有比Hf组成更高的Al的组成比，并且上部Hf x Al y O z薄膜具有较大的 Hf的组成比高于Al，上层Hf x Al y O z薄膜在沉积后在氧气氛下进行热处理。

10. 发明申请

US20070281454A1 Method of manufacturing semiconductor device for formation of pin transistor 有权
标题翻译：用于形成pin晶体管的半导体器件的制造方法
公开(公告)号：US20070281454A1
公开(公告)日：2007-12-06
申请号：US11647759
申请日：2006-12-29
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
IPC分类号： H01L21/3205
CPC分类号： H01L27/0886 , H01L27/1214
摘要： A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

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