专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070066008A1 METHOD OF FABRICATING NON-VOLATILE MEMORY 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20070066008A1
公开(公告)日：2007-03-22
申请号：US11558453
申请日：2006-11-10
申请人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
发明人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.
摘要翻译：描述了制造非易失性存储器的方法。在衬底上形成多个彼此间隙的第一存储单元。绝缘垫片形成在第一存储器单元的侧壁上。在衬底上形成复合层，并且第一存储单元之间的间隙填充有掺杂的多晶硅层。此后，去除掺杂多晶硅层的一部分以形成沟槽。之后，金属层填充沟槽。去除金属层的一部分以形成多个栅极。门和复合层一起形成多个第二存储单元。第二存储器单元和第一存储器单元一起构成存储单元列。然后，在与存储单元列的两侧相邻的基板中形成源极区域和漏极区域。

2. 发明授权

US07144774B1 Method of fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07144774B1
公开(公告)日：2006-12-05
申请号：US11162082
申请日：2005-08-29
申请人： Houng-Chi Wei , Saysamone Pittikoun
发明人： Houng-Chi Wei , Saysamone Pittikoun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , Y10S438/954
摘要： A method of fabricating a non-volatile memory includes providing a substrate having a composite dielectric layer, a sacrificial layer and a mask layer sequentially formed thereon. The mask layer is patterned to form a plurality of first openings for exposing a portion of the sacrificial layer. The sacrificial layer exposed by the first openings is removed and a plurality of first gates is formed in the first openings. The mask layer is further removed to form a plurality of second openings between the first gates. An insulating layer is formed on the tops and sidewalls of the first gates. A portion of the sacrificial layer exposed by the second openings is removed and a plurality of second gates is formed in the second openings. The second gates and the first gates embody a memory cell column. Source/region regions are formed in the substrate beside the memory cell column.
摘要翻译：一种制造非易失性存储器的方法包括提供具有在其上依次形成的复合介电层，牺牲层和掩模层的衬底。掩模层被图案化以形成用于暴露牺牲层的一部分的多个第一开口。去除由第一开口暴露的牺牲层，并且在第一开口中形成多个第一栅极。进一步去除掩模层以在第一栅极之间形成多个第二开口。绝缘层形成在第一栅极的顶部和侧壁上。去除由第二开口暴露的牺牲层的一部分，并且在第二开口中形成多个第二栅极。第二个门和第一个门体现了一个存储单元列。在存储单元列旁边的衬底中形成源极/区域区域。

3. 发明申请

US20060199333A1 Method of fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20060199333A1
公开(公告)日：2006-09-07
申请号：US11161648
申请日：2005-08-11
申请人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
发明人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.
摘要翻译：描述了制造非易失性存储器的方法。在衬底上形成多个彼此间隙的第一存储单元。在第一存储单元的侧壁上形成绝缘间隔物。在衬底上形成复合层，并且第一存储单元之间的间隙填充有掺杂的多晶硅层。此后，去除掺杂多晶硅层的一部分以形成沟槽。之后，金属层填充沟槽。去除金属层的一部分以形成多个栅极。门和复合层一起形成多个第二存储单元。第二存储器单元和第一存储器单元一起构成存储单元列。然后，在与存储单元列的两侧相邻的基板中形成源极区域和漏极区域。

4. 发明授权

US06232199B1 Method for forming a multi-cylinder capacitor 有权
标题翻译：多缸电容器的形成方法
公开(公告)号：US06232199B1
公开(公告)日：2001-05-15
申请号：US09588716
申请日：2000-06-07
申请人： Houng-chi Wei
发明人： Houng-chi Wei
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10852
摘要： The invention has disclosed a method for forming a multi-cylinder capacitor with simplified steps. First, first and second insulating layers are sequentially formed on a semiconductor substrate. Next, an alternate polysilicon layer is deposited. The alternate polysilicon layer includes a plurality of undoped polysilicon films alternating with a plurality of doped polysilicon films. Thereafter, a portion of said plurality of doped polysilicon films is selectively etched by utilizing the etching selectivity between said plurality of undoped and doped polysilicon films. Finally, the second insulating layer is removed and the undoped polysilicon films are doped to form multi-cylinder electrodes. According to the invention, the reliability of the multi-cylinder capacitor is improved and the cost of production is reduced. In addition, it is not necessary to add other steps if the number of cylindrical electrodes increases.
摘要翻译：本发明公开了一种用于形成具有简化步骤的多气缸电容器的方法。首先，在半导体衬底上依次形成第一绝缘层和第二绝缘层。接下来，沉积替代的多晶硅层。交替多晶硅层包括与多个掺杂多晶硅膜交替的多个未掺杂的多晶硅膜。此后，通过利用所述多个未掺杂和掺杂的多晶硅膜之间的蚀刻选择性来选择性地蚀刻所述多个掺杂多晶硅膜的一部分。最后，去除第二绝缘层，掺杂未掺杂多晶硅膜以形成多圆柱电极。根据本发明，提高了多气缸电容器的可靠性，降低了生产成本。此外，如果圆柱形电极的数量增加，则不需要添加其它步骤。

5. 发明授权

US6025245A Method of forming a trench capacitor with a sacrificial silicon nitrate sidewall 有权
标题翻译：用牺牲性硅酸盐侧壁形成沟槽电容器的方法
公开(公告)号：US6025245A
公开(公告)日：2000-02-15
申请号：US313668
申请日：1999-05-18
申请人： Houng-Chi Wei
发明人： Houng-Chi Wei
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. A bottom cell plate is formed in the lower trench region. The silicon nitride sidewall is removed. A dielectric film is formed along a surface of the bottom cell plate, the collar oxide, and the substrate, subsequently, a first conductive layer is formed on said dielectric film and refill in the trench region. The first conductive layer and the dielectric film are etched to the first level to expose a portion of the collar oxide, the exposed portion of the collar oxide is then etched by wet etching. A second conductive layer is formed on the first conductive layer and etched back to form a buried strap in the trench region.
摘要翻译：本发明提供一种用牺牲性氮化硅形成沟槽电容器的方法。在衬底中形成深沟槽结构。 TEOS氧化物层形成在衬底上并填充在所述沟槽区域中，随后蚀刻到第一层，其中TEOS氧化物层的一部分保留在沟槽区域中，并且衬底的一部分暴露以形成沟槽侧壁。进行热氧化处理以在暴露的基底上形成环状氧化物。在轴环氧化物上形成氮化硅侧壁，然后通过湿蚀刻去除残留的TEOS氧化物层。底部单元板形成在下部沟槽区域中。去除氮化硅侧壁。沿着底部单元板，轴环氧化物和基板的表面形成电介质膜，随后在所述介电膜上形成第一导电层并在沟槽区域中重新填充。将第一导电层和电介质膜蚀刻到第一层以暴露套环氧化物的一部分，然后通过湿蚀刻蚀刻环氧化物的暴露部分。第二导电层形成在第一导电层上并被回蚀刻以在沟槽区域中形成掩埋带。

6. 发明申请

US20080279001A1 OPERATING METHOD OF NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的操作方法
公开(公告)号：US20080279001A1
公开(公告)日：2008-11-13
申请号：US11927702
申请日：2007-10-30
申请人： Saysamone Pittikoun , Houng-Chi Wei , Chih-Chen Cho
发明人： Saysamone Pittikoun , Houng-Chi Wei , Chih-Chen Cho
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L29/42324 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate.
摘要翻译：提供具有多个存储单元的非易失性存储器，每个存储器单元包括选择单元和存储器单元。选择单元设置在基板上。存储单元设置在选择单元和基板的一个侧壁上。选择单元包括设置在基板上的栅极和设置在栅极和基板之间的第一栅极电介质层。所述存储单元包括设置在所述衬底上的一对浮置栅极，设置在所述浮置栅极的上表面上的控制栅极，设置在所述浮置栅极和所述控制栅极之间的栅极间电介质层，浮置栅极和衬底以及设置在控制栅极的底部和衬底之间的第二栅极电介质层。

7. 发明授权

US07445993B2 Method of fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07445993B2
公开(公告)日：2008-11-04
申请号：US11306254
申请日：2005-12-21
申请人： Wei-Chung Tseng , Houng-Chi Wei , Saysamone Pittikoun
发明人： Wei-Chung Tseng , Houng-Chi Wei , Saysamone Pittikoun
IPC分类号： H01L21/337
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.
摘要翻译：提供了一种制造非易失性存储器的方法。在基板的存储单元区域上形成多个第一存储单元。每个第一存储单元包括第一复合层，第一栅极和盖层。两个相邻的第一存储单元之间存在间隙。然后，在各个间隙中形成多个栅极。栅极与第二复合层一起形成多个第二存储单元。第二存储单元和第一存储单元一起构成存储单元列。同时，在外围电路区域也形成有多个栅极结构。使用不同的导电层制造间隙中的栅极和外围电路区域中的栅极。

8. 发明授权

US07285463B2 Method of fabricating non-volatile memory 有权
公开(公告)号：US07285463B2
公开(公告)日：2007-10-23
申请号：US11558453
申请日：2006-11-10
申请人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
发明人： Chien-Lung Chu , Saysamone Pittikoun , Houng-Chi Wei , Wei-Chung Tseng
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

9. 发明申请

US20090315096A1 NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090315096A1
公开(公告)日：2009-12-24
申请号：US12107787
申请日：2008-04-23
申请人： Houng-Chi Wei , Chien-Lung Chu , Saysamone Pittikoun
发明人： Houng-Chi Wei , Chien-Lung Chu , Saysamone Pittikoun
IPC分类号： H01L29/788 , H01L21/762 , H01L21/28
CPC分类号： H01L27/11531 , H01L21/76229 , H01L27/11521 , H01L27/11526 , H01L29/66825 , H01L29/7881
摘要： A method of manufacturing a non-volatile memory is provided. An insulating layer, a conductive material layer and a polish stop layer are sequentially on a substrate. Trenches are formed in a portion of the substrate, the polish stop layer, the conductive material layer and the insulating layer, and the conductive material layer is segmented to form conductive blocks. A dielectric material layer is formed to cover the polish stop layer and fill the trenches. A chemical mechanical polishing process is performed until exposing a surface of the polish stop layer. A portion of the dielectric layer is removed to form trench isolation structures. A portion of sidewalls of each conductive block is removed to form floating gates. A width of each floating gate is decreased gradually from bottom to top.
摘要翻译：提供一种制造非易失性存储器的方法。绝缘层，导电材料层和抛光停止层依次在基板上。在衬底的一部分，抛光停止层，导电材料层和绝缘层中形成沟槽，并且导电材料层被分段以形成导电块。形成介电材料层以覆盖抛光停止层并填充沟槽。执行化学机械抛光工艺直到暴露抛光停止层的表面。去除介电层的一部分以形成沟槽隔离结构。去除每个导电块的侧壁的一部分以形成浮动栅极。每个浮动门的宽度从底部到顶部逐渐减小。

10. 发明授权

US07442998B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07442998B2
公开(公告)日：2008-10-28
申请号：US11162648
申请日：2005-09-18
申请人： Houng-Chi Wei , Saysamone Pittikoun , Wei-Chung Tseng
发明人： Houng-Chi Wei , Saysamone Pittikoun , Wei-Chung Tseng
IPC分类号： H01L29/78
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.
摘要翻译：提供了一种制造非易失性存储器的方法。具有第一存储单元和第二存储单元的存储单元阵列形成在衬底上。然后，在存储单元阵列的各个侧面上的基板中形成源极区域和漏极区域。接下来，在基板上形成图案化的第一层间绝缘层，以形成第一沟槽和多个第二沟槽。导电层形成在基板上，以在第一沟槽中形成源极线，并在第二沟槽中形成导电线。在衬底上形成第二层间绝缘层，然后在第二层间绝缘层和第一层间绝缘层中形成与漏区接触的导电插塞。然后，在第二层间绝缘层上形成与导电插头接触的位线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式