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1. 发明授权

US06232199B1 Method for forming a multi-cylinder capacitor 有权
标题翻译：多缸电容器的形成方法
公开(公告)号：US06232199B1
公开(公告)日：2001-05-15
申请号：US09588716
申请日：2000-06-07
申请人： Houng-chi Wei
发明人： Houng-chi Wei
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10852
摘要： The invention has disclosed a method for forming a multi-cylinder capacitor with simplified steps. First, first and second insulating layers are sequentially formed on a semiconductor substrate. Next, an alternate polysilicon layer is deposited. The alternate polysilicon layer includes a plurality of undoped polysilicon films alternating with a plurality of doped polysilicon films. Thereafter, a portion of said plurality of doped polysilicon films is selectively etched by utilizing the etching selectivity between said plurality of undoped and doped polysilicon films. Finally, the second insulating layer is removed and the undoped polysilicon films are doped to form multi-cylinder electrodes. According to the invention, the reliability of the multi-cylinder capacitor is improved and the cost of production is reduced. In addition, it is not necessary to add other steps if the number of cylindrical electrodes increases.
摘要翻译：本发明公开了一种用于形成具有简化步骤的多气缸电容器的方法。首先，在半导体衬底上依次形成第一绝缘层和第二绝缘层。接下来，沉积替代的多晶硅层。交替多晶硅层包括与多个掺杂多晶硅膜交替的多个未掺杂的多晶硅膜。此后，通过利用所述多个未掺杂和掺杂的多晶硅膜之间的蚀刻选择性来选择性地蚀刻所述多个掺杂多晶硅膜的一部分。最后，去除第二绝缘层，掺杂未掺杂多晶硅膜以形成多圆柱电极。根据本发明，提高了多气缸电容器的可靠性，降低了生产成本。此外，如果圆柱形电极的数量增加，则不需要添加其它步骤。

2. 发明授权

US06423645B1 Method for forming a self-aligned contact 有权
标题翻译：形成自对准接触的方法
公开(公告)号：US06423645B1
公开(公告)日：2002-07-23
申请号：US09604559
申请日：2000-06-27
申请人： Houng-chi Wei , Tsong-lin Shen
发明人： Houng-chi Wei , Tsong-lin Shen
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31155 , H01L21/3148 , H01L21/3185 , Y10S438/97
摘要： The present invention discloses a method for forming a self-aligned contact. In the present invention, a amorphous SiC layer or a HexaChloroDisilane-SiN (HCD-SiN) layer is formed on the surface of a transistor as an etching stopper layer. After removing part of the etching stopper layer, a gate protection film is formed on the surface of the gate electrode of a transistor. Due to the high etching selectivity of the gate protection film to the dielectric layer, the gate protection film effectively prevents the gate electrode of a transistor from being etched in the contact-etching process. In addition, the gate protection film has a low dielectric constant thereby reducing the parasitic capacitance of a bit line formed by the self-aligned contact forming method according to the present invention.
摘要翻译：本发明公开了一种形成自对准接触的方法。在本发明中，在作为蚀刻停止层的晶体管的表面上形成无定形SiC层或六氯硅烷SiN（HCD-SiN）层。在去除部分蚀刻阻挡层之后，在晶体管的栅电极的表面上形成栅极保护膜。由于栅极保护膜对电介质层的高蚀刻选择性，栅极保护膜有效地防止在接触蚀刻工艺中蚀刻晶体管的栅电极。此外，栅极保护膜具有低介电常数，从而减小由根据本发明的自对准接触形成方法形成的位线的寄生电容。

3. 发明授权

US06251722B1 Method of fabricating a trench capacitor 有权
标题翻译：制造沟槽电容器的方法
公开(公告)号：US06251722B1
公开(公告)日：2001-06-26
申请号：US09546800
申请日：2000-04-11
申请人： Houng-chi Wei , Tso-chun Tony Wang
发明人： Houng-chi Wei , Tso-chun Tony Wang
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.
摘要翻译：提供了一种制造具有低于亚微米级的ULSI技术的高电容的沟槽电容器的方法。该方法包括：在半导体衬底上形成沟槽。沟槽在半导体衬底上具有底部和至少一个侧壁。然后，在硅衬底中形成用于包围沟槽的底部和其侧壁的预定区域的扩散层。之后，在沟槽的底部形成第一多晶硅层，并以第一多晶硅层的一部分不与侧壁接触的方式形成。然后，形成第一电介质层，以完全覆盖第一多晶硅层和扩散层。然后，在沟槽顶部形成上电极层，以至少完全覆盖第一电介质层。最终，扩散层和电介质层之间的接触面积大大增加，以便保持足够的电容。

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