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1. 发明申请

US20050030066A1 TRANSITION-AWARE SIGNALING 失效
标题翻译：过渡信号
公开(公告)号：US20050030066A1
公开(公告)日：2005-02-10
申请号：US10389320
申请日：2003-03-14
申请人： Dennis Sylvester , Himanshu Kaul
发明人： Dennis Sylvester , Himanshu Kaul
IPC分类号： H03K3/3565 , H03K5/08 , H03K5/1534 , H03K5/22 , H04L25/02
CPC分类号： H04L25/0292 , H03K3/3565 , H03K5/084 , H03K5/088 , H03K5/1534
摘要： An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a transition signal in response to a detection of a transition from a first state to a second state on the interconnect line and further generates the transition signal in response to a detection of a transition from the second state to the first state on said interconnect line. The receiver further includes an output signal control circuit that, in response to the transition signal, selectively outputs either a present state of said interconnect line or a next state of the interconnect line stored in the receiver.
摘要翻译：公开了一种用于集成芯片上的改进的接收机电路。接收器电路插入在集成电路中的电气部件之间的互连线中。接收器电路具有转换检测电路，其响应于在互连线上从第一状态到第二状态的转变的检测而产生转换信号，并且响应于检测到来自第二状态的转变而产生转换信号状态到所述互连线上的第一状态。接收机还包括输出信号控制电路，响应于转换信号，选择性地输出所述互连线的当前状态或存储在接收机中的互连线的下一状态。

2. 发明授权

US08103981B2 Tool for modifying mask design layout 有权
标题翻译：修改蒙版设计布局的工具
公开(公告)号：US08103981B2
公开(公告)日：2012-01-24
申请号：US12566925
申请日：2009-09-25
申请人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
发明人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.
摘要翻译：本发明的实施例提供了一种用于修改要印刷的掩模设计布局的工具。该工具由计算机系统执行，并且包括用于为掩模设计布局建立用于预定参数产量的第一级校正的代码，而不需要对掩模设计布局的区域进行校正的代价。该工具还包括用于基于校正算法在所述第一校正级别校正掩模设计布局的代码，所述校正算法选择具有针对单元中的每个门特征的边缘放置误差（EPE）的掩模设计布局的单元。校正算法选择不损失参数产量的单元，由参数产量确定。

3. 发明授权

US07614032B2 Method for correcting a mask design layout 有权
标题翻译：校正掩模设计布局的方法
公开(公告)号：US07614032B2
公开(公告)日：2009-11-03
申请号：US11637209
申请日：2006-12-11
申请人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
发明人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.
摘要翻译：用于执行掩模设计布局分辨率增强的方法包括以最小的总校正成本为预定参数产量确定设计布局的校正级别。如果需要校正，则基于校正算法在确定的校正水平校正设计布局。以这种方式，仅修改设计布局上对于获得期望的性能收益至关重要的印刷特征，从而降低了校正设计布局的总成本。

4. 发明申请

US20090138658A1 Cache memory system for a data processing apparatus 有权
标题翻译：用于数据处理装置的高速缓冲存储器系统
公开(公告)号：US20090138658A1
公开(公告)日：2009-05-28
申请号：US12292148
申请日：2008-11-12
申请人： Ronald George Dreslinski, JR. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
发明人： Ronald George Dreslinski, JR. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
摘要翻译：提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访问请求而耦合到高速缓冲存储器的高速缓存控制器。高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。还提供了相应的数据处理方法。

5. 发明授权

US07149999B2 Method for correcting a mask design layout 有权
标题翻译：校正掩模设计布局的方法
公开(公告)号：US07149999B2
公开(公告)日：2006-12-12
申请号：US10787070
申请日：2004-02-25
申请人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
发明人： Andrew B. Kahng , Puneet Gupta , Dennis Sylvester , Jie Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total correction cost. The mask design layout is corrected at a determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the mask design layout that are critical for obtaining a desired performance yield are corrected, thereby reducing total cost of correction of the mask design layout.
摘要翻译：用于执行掩模设计布局分辨率增强的方法包括以最小的总校正成本确定用于预定参数产量的掩模设计布局的校正级别。如果需要校正，则基于校正算法在确定的校正水平校正掩模设计布局。以这种方式，仅修正了掩模设计布局上对于获得期望的性能产出至关重要的打印特征，从而降低了掩模设计布局校正的总成本。

6. 发明申请

US20100327842A1 REFERENCE VOLTAGE GENERATOR HAVING A TWO TRANSISTOR DESIGN 有权
标题翻译：具有两个晶体管设计的参考电压发生器
公开(公告)号：US20100327842A1
公开(公告)日：2010-12-30
申请号：US12823160
申请日：2010-06-25
申请人： Mingoo Seok , Dennis Sylvester , David Blaauw , Scott Hanson , Gregory Chen
发明人： Mingoo Seok , Dennis Sylvester , David Blaauw , Scott Hanson , Gregory Chen
IPC分类号： G05F3/16
CPC分类号： G05F3/242
摘要： An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.
摘要翻译：提供改进的电压基准发生器。所述电压参考发生器包括：第一晶体管，具有被偏置以将所述第一晶体管置于弱反相模式的栅电极; 以及与所述第一晶体管串联连接的第二晶体管，并且具有被偏置以将所述第二晶体管置于弱反相模式的栅电极，其中所述第一晶体管的阈值电压小于所述第二晶体管和所述栅电极的阈值电压的第二晶体管的电极电耦合到第二晶体管的漏电极和第一晶体管的源电极，以形成用于参考电压的输出。

7. 发明申请

US20060018171A1 Memory system having fast and slow data reading mechanisms 有权
公开(公告)号：US20060018171A1
公开(公告)日：2006-01-26
申请号：US11150585
申请日：2005-06-13
申请人： Todd Austin , David Blaauw , Trevor Mudge , Dennis Sylvester , Krisztian Flautner
发明人： Todd Austin , David Blaauw , Trevor Mudge , Dennis Sylvester , Krisztian Flautner
IPC分类号： G11C7/00
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

8. 发明授权

US09147443B2 Low power reference current generator with tunable temperature sensitivity 有权
标题翻译：低功率参考电流发生器，具有可调温度敏感性
公开(公告)号：US09147443B2
公开(公告)日：2015-09-29
申请号：US13472870
申请日：2012-05-16
申请人： Scott Hanson , Dennis Sylvester , David Blaauw
发明人： Scott Hanson , Dennis Sylvester , David Blaauw
IPC分类号： H02M11/00 , G11C5/14 , G05F1/56 , G05F3/24
CPC分类号： G11C5/147 , G05F1/561 , G05F3/242
摘要： An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.
摘要翻译：提供改进的参考电流发生器。电压差发生器产生由相对小的电位分开的两个电压。两个紧密分离的电压施加在具有较大阻抗值的电阻元件上，导致小且稳定的参考电流。结果是功率有效的温度补偿参考电流发生器。

9. 发明授权

US08564275B2 Reference voltage generator having a two transistor design 有权
标题翻译：具有双晶体管设计的参考电压发生器
公开(公告)号：US08564275B2
公开(公告)日：2013-10-22
申请号：US12823160
申请日：2010-06-25
申请人： Mingoo Seok , Dennis Sylvester , David Blaauw , Scott Hanson , Gregory Chen
发明人： Mingoo Seok , Dennis Sylvester , David Blaauw , Scott Hanson , Gregory Chen
IPC分类号： G05F3/16
CPC分类号： G05F3/242
摘要： An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.
摘要翻译：提供改进的电压基准发生器。所述电压参考发生器包括：第一晶体管，具有被偏置以将所述第一晶体管置于弱反相模式的栅电极; 以及与所述第一晶体管串联连接的第二晶体管，并且具有被偏置以将所述第二晶体管置于弱反相模式的栅电极，其中所述第一晶体管的阈值电压小于所述第二晶体管和所述栅电极的阈值电压的第二晶体管的电极电耦合到第二晶体管的漏电极和第一晶体管的源电极，以形成用于参考电压的输出。

10. 发明授权

US08335122B2 Cache memory system for a data processing apparatus 有权
标题翻译：用于数据处理装置的高速缓冲存储器系统
公开(公告)号：US08335122B2
公开(公告)日：2012-12-18
申请号：US12292148
申请日：2008-11-12
申请人： Ronald George Dreslinski, Jr. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
发明人： Ronald George Dreslinski, Jr. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
IPC分类号： G11C5/14
CPC分类号： G06F12/0897 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
摘要翻译：提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访问请求而耦合到高速缓冲存储器的高速缓存控制器。高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。还提供了相应的数据处理方法。

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