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1. 发明授权

US08592887B2 Semiconductor storage device including a memory cell structure 有权
标题翻译：包括存储单元结构的半导体存储装置
公开(公告)号：US08592887B2
公开(公告)日：2013-11-26
申请号：US13332905
申请日：2011-12-21
申请人： Daina Inoue , Hidenobu Nagashima , Akira Yotsumoto
发明人： Daina Inoue , Hidenobu Nagashima , Akira Yotsumoto
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L21/764
摘要： A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.
摘要翻译：半导体存储装置包括设置在选择栅电极之间的层间绝缘膜，沿着存储单元栅电极的上部延伸的第一填充材料，以覆盖位于存储单元栅电极之间的空气间隙，第一填充材料沿着所述选择栅极电极和所述层间绝缘膜的侧壁，以便限定沿所述选择栅电极的侧壁和所述层间绝缘膜的侧壁延伸的所述第一填充材料上方的凹部，填充所述第一填充材料上方的所述凹部的第二填充材料填充材料和通过层间绝缘膜形成的多个触点，触点物理接触形成在半导体衬底中的每个器件区域。

2. 发明授权

US08294194B2 Nonvolatile semiconductor memory device and manufacturing method of the same 有权
标题翻译：非易失性半导体存储器件及其制造方法相同
公开(公告)号：US08294194B2
公开(公告)日：2012-10-23
申请号：US13052465
申请日：2011-03-21
申请人： Mitsuhiko Noda , Hidenobu Nagashima
发明人： Mitsuhiko Noda , Hidenobu Nagashima
IPC分类号： H01L21/76 , H01L29/788
CPC分类号： H01L27/11529 , H01L21/764 , H01L21/7682 , H01L29/42324
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储晶体管，层间绝缘膜，外围晶体管和侧壁。存储晶体管形成在半导体衬底上。每个存储晶体管包括第一堆叠栅极，其包括浮置栅电极，第二栅极绝缘膜和控制栅电极。层间绝缘膜形成在第一堆叠栅极之间。层间绝缘膜包括第一气隙。外围晶体管形成在基板上。外围晶体管包括第二堆叠栅极，其包括第一栅极电极，第三栅极绝缘膜和第二栅极电极。侧壁形成在第二堆叠门的侧表面上并且包括第二气隙。第二气隙的上端位于比第三栅极绝缘膜低的位置。

3. 发明申请

US20120241838A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120241838A1
公开(公告)日：2012-09-27
申请号：US13422547
申请日：2012-03-16
申请人： Hidenobu NAGASHIMA , Akira YOTSUMOTO
发明人： Hidenobu NAGASHIMA , Akira YOTSUMOTO
IPC分类号： H01L29/788 , H01L21/768
CPC分类号： H01L27/11524 , H01L21/76801 , H01L21/7682 , H01L21/76897
摘要： According to one embodiment, a semiconductor storage device includes: a plurality of word lines that are formed at predetermined intervals in a first direction on the element region; a select gate transistor that is arranged in each of both sides of the word lines and has a width in the first direction wider than the word line; a first air gap that is positioned between the word lines; and a second air gap that is formed on a side wall portion opposite to a side of the word line of the select gate transistor. Further, according to one embodiment, the semiconductor storage device is provided in which an oxide film is formed on a surface of a substrate between the select gate transistors that are adjacent to each other, and a cross-sectional surface in a direction perpendicular to the first direction under the oxide film has a convex shape.
摘要翻译：根据一个实施例，半导体存储装置包括：在元件区域上沿第一方向以预定间隔形成的多个字线; 选择栅极晶体管，其布置在字线的两侧中的每一侧中，并且在第一方向上的宽度比字线宽; 位于字线之间的第一气隙; 以及形成在与选择栅极晶体管的字线的一侧相对的侧壁部分上的第二气隙。此外，根据一个实施例，提供了一种半导体存储装置，其中在彼此相邻的选择栅极晶体管之间的衬底的表面上形成氧化物膜，并且在垂直于所述栅极晶体管的方向上的横截面氧化膜下的第一方向具有凸形。

4. 发明申请

US20120241833A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120241833A1
公开(公告)日：2012-09-27
申请号：US13422262
申请日：2012-03-16
申请人： Hidenobu NAGASHIMA
发明人： Hidenobu NAGASHIMA
IPC分类号： H01L29/788 , H01L21/762
CPC分类号： H01L29/7881 , H01L21/76224 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L29/42352
摘要： According to one embodiment, the storage device further includes: a first electrode that is formed in a reverse convex and in contact with an upper surface of a first region, parts of a side and an upper surface of a first isolation region that face a second isolation region, and parts of a side and an upper surface of the second isolation region that face the first isolation region; and a third electrode that is positioned in a different direction from a second direction with respect to the first electrode, formed in a reverse convex and in contact with an upper surface of a second region, parts of a side and the upper surface of the second isolation region that face a third isolation region, and parts of a side and an upper surface of the third isolation region that face the second isolation region.
摘要翻译：根据一个实施例，存储装置还包括：第一电极，其形成为反向凸起并与第一区域的上表面接触，第一隔离区域的侧面和上表面的面向第二区域的部分隔离区域以及面向第一隔离区域的第二隔离区域的侧面和上表面的部分; 以及第三电极，其相对于所述第一电极相对于与所述第一电极相反的第二方向位于不同的方向上，形成为反向凸起并与第二区域的上表面接触，所述第二电极的侧面的一部分和所述第二电极的上表面隔离区域，以及面对第二隔离区域的第三隔离区域的侧面和上表面的部分。

5. 发明授权

US09030020B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09030020B2
公开(公告)日：2015-05-12
申请号：US13053671
申请日：2011-03-22
申请人： Yoshiko Kato , Hidenobu Nagashima
发明人： Yoshiko Kato , Hidenobu Nagashima
IPC分类号： H01L23/48 , G11C16/04 , G11C5/06 , H01L27/02 , H01L27/115
CPC分类号： G11C16/0483 , G11C5/063 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.
摘要翻译：在一个实施例中，半导体存储器件包括衬底，以及形成在衬底中的器件区域，其在与衬底的主平面平行的第一方向上延伸。该装置还包括设置在基板上的选择栅极，其在与第一方向垂直的第二方向上延伸，以及设置在基板上的选择栅极之间并包括设置在各个器件区域上的接触插塞的接触区域。此外，接触区域包括部分区域，其中每个N个接触插塞设置在N个连续的器件区域上，以布置在不平行于第一和第二方向的直线上，其中N是2或更大的整数。此外，接触区域包括N值不同的至少两种类型的部分区域。

6. 发明申请

US20120244696A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120244696A1
公开(公告)日：2012-09-27
申请号：US13428046
申请日：2012-03-23
申请人： Hidenobu NAGASHIMA
发明人： Hidenobu NAGASHIMA
IPC分类号： H01L21/3213
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/32139 , H01L27/11524 , H01L29/40114 , H01L29/42324
摘要： A method of manufacturing a semiconductor device is disclosed. The method includes forming a third film so as to cover a second pattern, a second mask pattern, and a first film; etching back the third film to form a first sidewall line pattern along a sidewall of the second pattern and to form a first sidewall mask pattern along a sidewall of the second mask pattern; forming a third mask pattern comprising a resist film so as to cover the second mask pattern and the first sidewall mask pattern; and selectively removing the second pattern using the third mask pattern as a mask and thereafter removing the third mask pattern.
摘要翻译：公开了制造半导体器件的方法。该方法包括形成第三膜以覆盖第二图案，第二掩模图案和第一膜; 蚀刻第三膜以沿着第二图案的侧壁形成第一侧壁线图案，并沿着第二掩模图案的侧壁形成第一侧壁掩模图案; 形成包括抗蚀剂膜以覆盖第二掩模图案和第一侧壁掩模图案的第三掩模图案; 并使用第三掩模图案作为掩模选择性地去除第二图案，然后除去第三掩模图案。

7. 发明申请

US20120018780A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120018780A1
公开(公告)日：2012-01-26
申请号：US13075665
申请日：2011-03-30
申请人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
发明人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/11521
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。该方法可以包括形成覆盖栅电极的侧面的保护膜。该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。栅电极的侧面被保护膜覆盖。该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。

8. 发明授权

US08723245B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08723245B2
公开(公告)日：2014-05-13
申请号：US13052531
申请日：2011-03-21
申请人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
发明人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/11521
摘要： According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.
摘要翻译：根据一个实施例，非易失性存储器件包括衬底，第一和第二隧道绝缘膜，第一和第二浮栅电极，栅间绝缘膜和控制栅电极。衬底具有通过元件隔离沟槽彼此隔离的第一和第二有源区。第一和第二隧道绝缘膜分别位于第一和第二有源区中。第一和第二浮栅电极分别位于第一和第二隧道绝缘膜上。隔间绝缘膜包括第一绝缘材料的第一绝缘层，第一绝缘层上的第二绝缘材料的电子陷阱层和电子陷阱层上的第一绝缘材料的第二绝缘层。控制栅电极位于隔间绝缘膜上。

9. 发明申请

US20120119368A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120119368A1
公开(公告)日：2012-05-17
申请号：US13053671
申请日：2011-03-22
申请人： Yoshiko KATO , Hidenobu Nagashima
发明人： Yoshiko KATO , Hidenobu Nagashima
IPC分类号： H01L23/48
CPC分类号： G11C16/0483 , G11C5/063 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.
摘要翻译：在一个实施例中，半导体存储器件包括衬底，以及形成在衬底中的器件区域，其在与衬底的主平面平行的第一方向上延伸。该装置还包括设置在基板上的选择栅极，其在与第一方向垂直的第二方向上延伸，以及设置在基板上的选择栅极之间并包括设置在各个器件区域上的接触插塞的接触区域。此外，接触区域包括部分区域，其中每个N个接触插塞设置在N个连续的器件区域上，以布置在不平行于第一和第二方向的直线上，其中N是2或更大的整数。此外，接触区域包括N值不同的至少两种类型的部分区域。

10. 发明申请

US20120256263A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120256263A1
公开(公告)日：2012-10-11
申请号：US13332905
申请日：2011-12-21
申请人： Daina INOUE , Hidenobu Nagashima , Akira Yotsumoto
发明人： Daina INOUE , Hidenobu Nagashima , Akira Yotsumoto
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/11524 , H01L21/764
摘要： A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.
摘要翻译：半导体存储装置包括设置在选择栅电极之间的层间绝缘膜，沿着存储单元栅电极的上部延伸的第一填充材料，以覆盖位于存储单元栅电极之间的空气间隙，第一填充材料沿着所述选择栅极电极和所述层间绝缘膜的侧壁，以便限定沿所述选择栅电极的侧壁和所述层间绝缘膜的侧壁延伸的所述第一填充材料上方的凹部，填充所述第一填充材料上方的所述凹部的第二填充材料填充材料和通过层间绝缘膜形成的多个触点，触点物理接触形成在半导体衬底中的每个器件区域。

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