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1. 发明申请

US20090286389A1 METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权
标题翻译：利用现场清洁优化硅酸盐污染物尺寸的方法
公开(公告)号：US20090286389A1
公开(公告)日：2009-11-19
申请号：US12122840
申请日：2008-05-19
申请人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
发明人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28052 , H01L29/6653 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离地区。侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

2. 发明申请

US20090090969A1 ELECTRONIC DEVICE AND METHOD OF BIASING 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US20090090969A1
公开(公告)日：2009-04-09
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

3. 发明授权

US06255215B1 Semiconductor device having silicide layers formed using a collimated metal layer 有权
标题翻译：具有使用准直金属层形成的硅化物层的半导体器件
公开(公告)号：US06255215B1
公开(公告)日：2001-07-03
申请号：US09175652
申请日：1998-10-20
申请人： Fred Hause , Charles E. May , William S. Brennan
发明人： Fred Hause , Charles E. May , William S. Brennan
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.
摘要翻译：提供了使用通过准直沉积形成的金属层形成硅化物层的工艺。准直金属层可以例如通过溅射金属颗粒并在形成金属层之前过滤金属颗粒来形成。通过以这种方式沉积金属，与使用常规技术形成的金属硅化物层相比，所得金属硅化物层的电阻可以降低。也可以采用较低的硅化反应温度。

4. 发明授权

US6117742A Method for making a high performance transistor 失效
标题翻译：制造高性能晶体管的方法
公开(公告)号：US6117742A
公开(公告)日：2000-09-12
申请号：US079760
申请日：1998-05-15
申请人： Mark I. Gardner , Fred Hause
发明人： Mark I. Gardner , Fred Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/2815 , H01L21/823437 , H01L29/66659 , H01L29/4966
摘要： The present invention is directed to a method for manufacturing a semiconductor device having a reduced feature size and improved electrical performance characteristics. The method includes forming at least one masking layer and forming an opening in said masking layer. The method further includes forming a metal layer above at least a portion of said masking layer and removing said masking layer to define a gate electrode comprised of a portion of said metal layer. The method also includes removing the masking layer to expose portions of the surface of the substrate and doping the exposed portions of the substrate to define at least one source or drain region.
摘要翻译：本发明涉及一种具有减小的特征尺寸和改善的电性能特性的半导体器件的制造方法。该方法包括形成至少一个掩模层并在所述掩模层中形成开口。该方法还包括在所述掩模层的至少一部分上形成金属层，并去除所述掩模层以限定由所述金属层的一部分组成的栅电极。该方法还包括去除掩模层以暴露衬底表面的部分并掺杂衬底的暴露部分以限定至少一个源极或漏极区域。

5. 发明授权

US06043533A Method of integrating Ldd implantation for CMOS device fabrication 失效
标题翻译：整合Ldd植入用于CMOS器件制造的方法
公开(公告)号：US06043533A
公开(公告)日：2000-03-28
申请号：US944377
申请日：1997-10-06
申请人： Mark I. Gardner , Fred Hause , Robert Paiz
发明人： Mark I. Gardner , Fred Hause , Robert Paiz
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件制造的轻掺杂漏极注入的集成方法包括提供具有p阱区域和n-阱区域的半导体衬底。在p阱区域和n阱区域中的每一个上形成图案化栅极氧化物和栅极电极。使用具有规定厚度的图案化光致抗蚀剂掩蔽p阱区域或n阱区域中的一个，留下未被掩蔽的区域。然后植入离子以在n阱区域中形成期望的p型轻掺杂漏极（Pldd）区域，包括与n阱区域中的栅电极的边缘相邻的Pldd区域。最后，注入离子以在p阱区域中形成期望的n型轻掺杂漏极（Nldd）区域，包括与p阱区域中的栅电极的边缘相邻的Nldd区域，从而形成Pldd和Nldd区域仅使用单个离子注入掩模步骤。还公开了半导体衬底和集成电路。

6. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

7. 发明授权

US6080640A Metal attachment method and structure for attaching substrates at low temperatures 失效
标题翻译：用于在低温下安装基板的金属附着方法和结构
公开(公告)号：US6080640A
公开(公告)日：2000-06-27
申请号：US45324
申请日：1998-03-20
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/768 , H01L21/98 , H01L23/532 , H01L25/065 , H01L21/30 , H01L21/46
CPC分类号： H01L25/50 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L24/80 , H01L25/0657 , H01L2224/05571 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011
摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from is the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.
摘要翻译：高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构实施和设置在其顶表面上的金属层间线。第一衬底结构包括布置在金属层间线之间的平坦化低K电介质和将金属层间线与低K电介质隔开的保护涂层，第一硅衬底结构的金属层间线具有在介电K值在2.0-3.8范围内的低K电介质。第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度并且介电K值在2.0-3.8范围内的低K电介质。最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

8. 发明授权

US5952702A High performance MOSFET structure having asymmetrical spacer formation and having source and drain regions with different doping concentration 失效
标题翻译：具有不对称间隔物形成并且具有不同掺杂浓度的源极和漏极区的高性能MOSFET结构
公开(公告)号：US5952702A
公开(公告)日：1999-09-14
申请号：US944372
申请日：1997-10-06
申请人： Mark I. Gardner , Fred Hause
发明人： Mark I. Gardner , Fred Hause
IPC分类号： H01L21/336 , H01L29/78 , H01L29/10
CPC分类号： H01L29/66659 , H01L29/6656 , H01L29/7835
摘要： A method of fabricating a field effect transistor (FET) having an asymmetrical spacer formation includes the steps of forming a gate oxide and a gate electrode on a semiconductor material of a first conductivity type. The gate electrode includes a first and second side edges proximate first and second regions, respectively, of the semiconductor material. Ions of a second conductivity type are implanted to form lightly doped regions extending at least between the first side edge and the first region and at least between the second side edge and the second region, respectively. Blanket layers of oxide and nitride are then formed on the gate electrode and the semiconductor material. The nitride layer is patterned and a first sidewall spacer is formed in a remaining portion of the nitride layer proximate the second side edge. A second blanket layer of oxide is then formed on the first oxide layer and first sidewall spacer. Lastly, second sidewall spacers are formed in the second oxide layer, wherein a first one of the second sidewall spacers includes oxide of a first lateral dimension proximate the first side edge and wherein a second one of the second sidewall spacers is juxtaposed with the first sidewall spacer to form a composite sidewall spacer of a second lateral dimension greater than the first lateral dimension. A novel FET is disclosed also.
摘要翻译：制造具有不对称间隔物形成的场效应晶体管（FET）的方法包括以下步骤：在第一导电类型的半导体材料上形成栅极氧化物和栅电极。栅极电极包括分别靠近半导体材料的第一和第二区域的第一和第二侧边缘。植入第二导电类型的离子以形成至少在第一侧边缘和第一区域之间以及至少在第二侧边缘和第二区域之间延伸的轻掺杂区域。然后在栅电极和半导体材料上形成氧化物层和氮化物层。图案化氮化物层，并且第一侧壁间隔物形成在靠近第二侧边缘的氮化物层的剩余部分中。然后在第一氧化物层和第一侧壁间隔物上形成第二覆盖层氧化物。最后，第二侧壁间隔物形成在第二氧化物层中，其中第二侧壁间隔物中的第一侧壁间隔物包括靠近第一侧边缘的第一侧向尺寸的氧化物，并且其中第二侧壁间隔物中的第二侧壁间隔物与第一侧壁并置间隔件以形成大于第一横向尺寸的第二横向尺寸的复合侧壁间隔件。还公开了一种新颖的FET。

9. 发明授权

US5841168A High performance asymmetrical MOSFET structure and method of making the same 失效
标题翻译：高性能非对称MOSFET结构及其制作方法
公开(公告)号：US5841168A
公开(公告)日：1998-11-24
申请号：US934509
申请日：1997-09-19
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66659 , H01L29/7835 , H01L29/6656 , Y10S257/90
摘要： A method of fabricating a high performance asymmetrical field effect transistor (FET)includes the steps of forming a gate oxide and a gate electrode on a layer of semiconductor material of a first conductivity type. The gate electrode includes a first side edge adjacent a first region of the semiconductor material and a second side edge proximate a second region of the semiconductor material. First and second lightly doped regions are formed in regions of the semiconductor material not covered by the gate oxide, and extending away from the first and second side edges of the gate electrode, respectively. First and second sidewall spacers are formed proximate the first and second side edges of the gate electrode, respectively, each sidewall spacer including a composite sidewall spacer of a first and a second spacer material. Lastly, a very highly doped source region and a highly doped drain region are formed in the first and second regions, respectively, the very highly doped source region having a greater dopant concentration of the second conductivity type than the highly doped drain region and the highly doped drain region having a dopant concentration greater than the lightly doped region extending away from the second side edge of said gate electrode. A novel FET is disclosed also.
摘要翻译：制造高性能不对称场效应晶体管（FET）的方法包括在第一导电类型的半导体材料层上形成栅极氧化物和栅电极的步骤。栅电极包括与半导体材料的第一区域相邻的第一侧边缘和靠近半导体材料的第二区域的第二侧边缘。第一和第二轻掺杂区域形成在半导体材料未被栅极氧化物覆盖的区域中，并且分别从栅电极的第一和第二侧边缘延伸。第一和第二侧壁间隔物分别形成在栅电极的第一和第二侧边缘附近，每个侧壁间隔物包括第一和第二间隔物材料的复合侧壁间隔物。最后，分别在第一和第二区域中形成非常高掺杂的源极区和高掺杂的漏极区，非常高掺杂的源极区具有比高掺杂漏极区高的掺杂浓度的第二导电类型，掺杂浓度的漏极区域的掺杂浓度大于远离所述栅电极的第二侧边缘延伸的轻掺杂区域。还公开了一种新颖的FET。

10. 发明授权

US5747852A LDD MOS transistor with improved uniformity and controllability of alignment 失效
标题翻译： LDD MOS晶体管具有改进的均匀性和对准的可控性
公开(公告)号：US5747852A
公开(公告)日：1998-05-05
申请号：US861190
申请日：1997-05-21
申请人： K. Y. Chang , Mark I. Gardner , Fred Hause
发明人： K. Y. Chang , Mark I. Gardner , Fred Hause
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/823814 , Y10S257/90
摘要： A MOS integrated circuit device fabricated utilizing high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a lightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rather than two mask and etch operations which are necessary using a conventional process.
摘要翻译：该MOS集成电路器件利用高能量，高电流注入离子通过一层氧化物制造，以形成与多晶硅栅极自对准的重掺杂源极和漏极区。与多晶硅栅极相邻的氧化物层的厚部分防止在栅极旁边的衬底中的重掺杂。去除氧化物层，轻掺杂漏极（LDD）注入形成与栅极自对准的LDD区域。使用该方法，仅使用单个掩模和蚀刻操作来执行源/漏极和LDD注入，而不是使用常规工艺所必需的两个掩模和蚀刻操作。

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