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1. 发明申请

US20090090969A1 ELECTRONIC DEVICE AND METHOD OF BIASING 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US20090090969A1
公开(公告)日：2009-04-09
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

2. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

3. 发明授权

US6027859A Semiconductor substrate having extended scribe line test structure and method of fabrication thereof 失效
标题翻译：具有延长的划片线测试结构的半导体衬底及其制造方法
公开(公告)号：US6027859A
公开(公告)日：2000-02-22
申请号：US992234
申请日：1997-12-17
申请人： Robert Dawson , Mark W. Michael , Fred Hause
发明人： Robert Dawson , Mark W. Michael , Fred Hause
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F7/70475
摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.
摘要翻译：本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案，部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。第一和第二测试结构图案可以例如形成在基板的划线中。

4. 发明申请

US20090286389A1 METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权
标题翻译：利用现场清洁优化硅酸盐污染物尺寸的方法
公开(公告)号：US20090286389A1
公开(公告)日：2009-11-19
申请号：US12122840
申请日：2008-05-19
申请人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
发明人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28052 , H01L29/6653 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离地区。侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

5. 发明授权

US06255215B1 Semiconductor device having silicide layers formed using a collimated metal layer 有权
标题翻译：具有使用准直金属层形成的硅化物层的半导体器件
公开(公告)号：US06255215B1
公开(公告)日：2001-07-03
申请号：US09175652
申请日：1998-10-20
申请人： Fred Hause , Charles E. May , William S. Brennan
发明人： Fred Hause , Charles E. May , William S. Brennan
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.
摘要翻译：提供了使用通过准直沉积形成的金属层形成硅化物层的工艺。准直金属层可以例如通过溅射金属颗粒并在形成金属层之前过滤金属颗粒来形成。通过以这种方式沉积金属，与使用常规技术形成的金属硅化物层相比，所得金属硅化物层的电阻可以降低。也可以采用较低的硅化反应温度。

6. 发明授权

US6117742A Method for making a high performance transistor 失效
标题翻译：制造高性能晶体管的方法
公开(公告)号：US6117742A
公开(公告)日：2000-09-12
申请号：US079760
申请日：1998-05-15
申请人： Mark I. Gardner , Fred Hause
发明人： Mark I. Gardner , Fred Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/2815 , H01L21/823437 , H01L29/66659 , H01L29/4966
摘要： The present invention is directed to a method for manufacturing a semiconductor device having a reduced feature size and improved electrical performance characteristics. The method includes forming at least one masking layer and forming an opening in said masking layer. The method further includes forming a metal layer above at least a portion of said masking layer and removing said masking layer to define a gate electrode comprised of a portion of said metal layer. The method also includes removing the masking layer to expose portions of the surface of the substrate and doping the exposed portions of the substrate to define at least one source or drain region.
摘要翻译：本发明涉及一种具有减小的特征尺寸和改善的电性能特性的半导体器件的制造方法。该方法包括形成至少一个掩模层并在所述掩模层中形成开口。该方法还包括在所述掩模层的至少一部分上形成金属层，并去除所述掩模层以限定由所述金属层的一部分组成的栅电极。该方法还包括去除掩模层以暴露衬底表面的部分并掺杂衬底的暴露部分以限定至少一个源极或漏极区域。

7. 发明授权

US06043533A Method of integrating Ldd implantation for CMOS device fabrication 失效
标题翻译：整合Ldd植入用于CMOS器件制造的方法
公开(公告)号：US06043533A
公开(公告)日：2000-03-28
申请号：US944377
申请日：1997-10-06
申请人： Mark I. Gardner , Fred Hause , Robert Paiz
发明人： Mark I. Gardner , Fred Hause , Robert Paiz
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件制造的轻掺杂漏极注入的集成方法包括提供具有p阱区域和n-阱区域的半导体衬底。在p阱区域和n阱区域中的每一个上形成图案化栅极氧化物和栅极电极。使用具有规定厚度的图案化光致抗蚀剂掩蔽p阱区域或n阱区域中的一个，留下未被掩蔽的区域。然后植入离子以在n阱区域中形成期望的p型轻掺杂漏极（Pldd）区域，包括与n阱区域中的栅电极的边缘相邻的Pldd区域。最后，注入离子以在p阱区域中形成期望的n型轻掺杂漏极（Nldd）区域，包括与p阱区域中的栅电极的边缘相邻的Nldd区域，从而形成Pldd和Nldd区域仅使用单个离子注入掩模步骤。还公开了半导体衬底和集成电路。

8. 发明申请

US20100164093A1 HEAT DISSIPATION IN TEMPERATURE CRITICAL DEVICE AREAS OF SEMICONDUCTOR DEVICES BY HEAT PIPES CONNECTING TO THE SUBSTRATE BACKSIDE 有权
标题翻译：通过连接到底板背面的热管连接半导体器件的温度关键装置区域的散热
公开(公告)号：US20100164093A1
公开(公告)日：2010-07-01
申请号：US12642989
申请日：2009-12-21
申请人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
发明人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
IPC分类号： H01L23/36 , H01L21/00
CPC分类号： H01L23/427 , H01L23/3677 , H01L23/481 , H01L23/522 , H01L27/16 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.
摘要翻译：通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。

9. 发明申请

US20100102363A1 AIR GAP SPACER FORMATION 有权
标题翻译：空气隙间隙形成
公开(公告)号：US20100102363A1
公开(公告)日：2010-04-29
申请号：US12258188
申请日：2008-10-24
申请人： Fred Hause , Anthony C. Mowry , David G. Farber , Markus E. Lenski
发明人： Fred Hause , Anthony C. Mowry , David G. Farber , Markus E. Lenski
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
摘要翻译：小型化的复合晶体管器件形成有减少的泄漏和减小的磨机电容。实施例包括通过利用低K介电常数侧壁间隔物材料在栅电极和源极/漏极接触之间具有减小的电容的晶体管。一个实施例包括在半导体衬底上形成栅电极，在栅电极的侧表面上形成侧壁间隔物，通过离子注入形成源/漏区，在栅电极，侧壁间隔物和衬底上形成层间电介质，以及通过层间电介质形成源/漏接触。然后去除侧壁间隔物和层间电介质。然后将诸如低K电介质材料的电介质材料沉积在栅电极和源极/漏极接触之间的间隙中，从而形成气隙，由此减小寄生“铣”电容。

10. 发明授权

US07279367B1 Method of manufacturing a thyristor semiconductor device 失效
标题翻译：晶闸管半导体器件的制造方法
公开(公告)号：US07279367B1
公开(公告)日：2007-10-09
申请号：US11007510
申请日：2004-12-07
申请人： Andrew E. Horch , Fred Hause
发明人： Andrew E. Horch , Fred Hause
IPC分类号： H01L21/332
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/823835 , H01L27/1027 , H01L27/1203 , H01L29/66378
摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.
摘要翻译：在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。在另一实施例中，植入物可以限定到晶闸管器件的基极区域。可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

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