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1. 发明申请

US20120278374A1 Decimal Floating-Point Quantum Exception Detection 审中-公开
标题翻译：十进制浮点量子异常检测
公开(公告)号：US20120278374A1
公开(公告)日：2012-11-01
申请号：US13544338
申请日：2012-07-09
申请人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
发明人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

2. 发明授权

US08219605B2 Decimal floating-pointing quantum exception detection 有权
标题翻译：十进制浮点量子异常检测
公开(公告)号：US08219605B2
公开(公告)日：2012-07-10
申请号：US12789765
申请日：2010-05-28
申请人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
发明人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

3. 发明授权

US08082467B2 Triggering workaround capabilities based on events active in a processor pipeline 有权
标题翻译：根据处理器管道中活动的事件触发解决方法的功能
公开(公告)号：US08082467B2
公开(公告)日：2011-12-20
申请号：US12645771
申请日：2009-12-23
申请人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
摘要翻译：公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。从存储器位置获取至少一个指令。该指令被解码。与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

4. 发明申请

US20110296229A1 DECIMAL FLOATING-POINTING QUANTUM EXCEPTION DETECTION 有权
标题翻译：十进制浮点数量子例外检测
公开(公告)号：US20110296229A1
公开(公告)日：2011-12-01
申请号：US12789765
申请日：2010-05-28
申请人： MICHAEL F. COWLISHAW , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
发明人： MICHAEL F. COWLISHAW , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
IPC分类号： G06F11/07
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

5. 发明申请

US20110219213A1 INSTRUCTION CRACKING BASED ON MACHINE STATE 有权
标题翻译：基于机器的指导性破碎
公开(公告)号：US20110219213A1
公开(公告)日：2011-09-08
申请号：US12718685
申请日：2010-03-05
申请人： Fadi BUSABA , Bruce GIAMEI , David HUTTON , Eric SCHWARZ
发明人： Fadi BUSABA , Bruce GIAMEI , David HUTTON , Eric SCHWARZ
IPC分类号： G06F9/30
CPC分类号： G06F9/342 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30189
摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.
摘要翻译：一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。至少接收一条指令。至少一条指令被解码。响应于解码确定当前机器状态。基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。执行一组操作单元。

6. 发明申请

US20110153991A1 DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS 有权
标题翻译：复杂指令设置指令的双重发布
公开(公告)号：US20110153991A1
公开(公告)日：2011-06-23
申请号：US12645716
申请日：2009-12-23
申请人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译：一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。指令发布单元向第一执行单元发出第一微操作以产生中间数据。然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。在延迟之后，向第二执行单元发出第二个微操作。

7. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

8. 发明申请

US20060179091A1 System and method for performing decimal to binary conversion 有权
标题翻译：用于执行十进制到二进制转换的系统和方法
公开(公告)号：US20060179091A1
公开(公告)日：2006-08-10
申请号：US11054233
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。运行总和和运行进位设置为零。对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

9. 发明申请

US20060173946A1 Common shift-amount calculation for binary and hex floating point 失效
标题翻译：二进制和十六进制浮点的通用移位量计算
公开(公告)号：US20060173946A1
公开(公告)日：2006-08-03
申请号：US11341256
申请日：2006-01-26
申请人： Son Trong , Juergen Haess , Klaus Kroener , Eric Schwarz
发明人： Son Trong , Juergen Haess , Klaus Kroener , Eric Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3812
摘要： A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC−expB+CV).
摘要翻译：一种用于执行二进制模式和十六进制模式的方法和系统根据公式A * C + B在浮点算术单元中乘法 - 浮点运算，其中A，B和C操作数各自具有分数和指数部分expA ，expB和expC和乘积A * C的指数被计算，并且与包含专用于使用无符号偏移指数的指数偏差值的加数指数进行比较，其中比较产生用于将加数与产品操作数，其中移位量计算根据公式（expA + expC-expB + CV）为二进制和十六进制提供公共值CV。

10. 发明授权

US4225244A Device for indicating fibre length distribution of a fibre sample 失效
标题翻译：用于指示纤维样品的纤维长度分布的装置
公开(公告)号：US4225244A
公开(公告)日：1980-09-30
申请号：US899883
申请日：1978-04-25
申请人： Eric Schwarz
发明人： Eric Schwarz
IPC分类号： G01D21/00 , G01B11/02 , G01N21/00 , D01B3/04 , G01B11/00 , G01N21/84
CPC分类号： G01B11/02
摘要： A device for indicating the fibre length distribution of a fibre sample for use with an apparatus which produces output signals representative of the number of fibres in a cross section of a fibre sample by slit-wise illumination of the sample, has a pulse generator to produce a pulse stream representative of the relative positions of the sample and illuminating beam, comparators to compare signals received by opto-electric converter with reference signals to stop counters driven by the pulse stream when predetermined values of the received signals are reached and an indicator for the contents of the counters. The reference signals are derived from the received light signals at predetermined relative positions of the sample and beams.
摘要翻译：用于指示纤维样品的纤维长度分布的装置，其用于产生表示纤维样品的横截面中的纤维数量的输出信号的装置，所述装置通过样品的狭缝照明而具有脉冲发生器，以产生表示采样和照明光束的相对位置的脉冲流，比较器，用于将光电转换器接收的信号与参考信号进行比较，以在达到接收信号的预定值时停止由脉冲流驱动的计数器，并且指示器柜台的内容参考信号是从样品和光束的预定相对位置处的接收光信号导出的。

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