专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180226986A1 CODING METHOD, CODING DEVICE, DECODING METHOD, AND DECODING DEVICE 审中-公开
公开(公告)号：US20180226986A1
公开(公告)日：2018-08-09
申请号：US15940081
申请日：2018-03-29
申请人： FUJITSU LIMITED
发明人： Masahiro KATAOKA
IPC分类号： H03M7/12 , H03M7/40
CPC分类号： H03M7/12 , H03M7/40 , H03M7/4037 , H03M7/4068
摘要： A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2n representation of the numerical value to be coded, wherein “n” is a natural number equal to or greater than 1.

2. 发明授权

US09778906B2 Apparatus and method for performing conversion operation 有权
公开(公告)号：US09778906B2
公开(公告)日：2017-10-03
申请号：US14582875
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/48 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value.

3. 发明授权

US09766858B2 Vector operands with component representing different significance portions 有权
公开(公告)号：US09766858B2
公开(公告)日：2017-09-19
申请号：US14582968
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F9/30 , G06F7/48 , G06F9/38 , G06F11/34 , G06F11/36 , G06F7/38 , G06F17/16 , G06F5/01 , G06F7/483 , G06F7/499 , H03M7/12 , H03M7/24 , G06F7/507 , G06F7/49 , G06F7/50 , G06F7/12 , G06F7/24 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.

4. 发明授权

US09766857B2 Data processing apparatus and method using programmable significance data 有权
公开(公告)号：US09766857B2
公开(公告)日：2017-09-19
申请号：US14582836
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F7/48 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus includes processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.

5. 发明申请

US20140101215A1 DPD/BCD TO BID CONVERTERS 有权
标题翻译： DPD / BCD转换器
公开(公告)号：US20140101215A1
公开(公告)日：2014-04-10
申请号：US13644374
申请日：2012-10-04
申请人： Ahmed A. Ayoub , Hossam Aly Hassan Fahmy , Tarek Eldeeb
发明人： Ahmed A. Ayoub , Hossam Aly Hassan Fahmy , Tarek Eldeeb
IPC分类号： G06F7/38
CPC分类号： H03M7/02 , H03M7/12
摘要： A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors.
摘要翻译：二进制编码十进制（BCD）到二进制转换的方法和系统。转换包括获得对应于多个十进制数字的BCD有效位数; 通过BCD /二进制硬件转换器和基于BCD有效位数生成对应于多个十进制数字的多个二进制向量; 并且由BCD /二进制硬件转换器通过对多个二进制向量求和来计算二进制输出。

6. 发明申请

US20100306632A1 ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL AND DENSELY PACKED DECIMAL CONVERSIONS 失效
标题翻译：在二进制编码的十进制和密封包装的十进制转换中使用奇偶校验的错误检测
公开(公告)号：US20100306632A1
公开(公告)日：2010-12-02
申请号：US12472519
申请日：2009-05-27
申请人： Steven R. Carlough , Mark A. Erle , Michael R. Kelly
发明人： Steven R. Carlough , Mark A. Erle , Michael R. Kelly
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M7/12 , H03M13/09
摘要： Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.
摘要翻译：使用二进制编码十进制（BCD）和密集十进制（DPD）转换中的奇偶校验的误差检测，包括具有由处理电路可读的有形存储介质的计算机程序产品，并且存储由处理电路执行以执行方法的指令。该方法包括以第一格式接收格式化的十进制数据，格式化的十进制数据由DPD格式数据或BCD格式数据组成。通过将接收到的数据转换成格式化的十进制数据的第二格式，并且通过确定第二格式的数据的奇偶校验来生成一个或多个第一奇偶校验位。从接收的数据直接生成一个或多个第二奇偶校验位。响应于第一奇偶校验位不等于第二奇偶校验位，错误标志被设置为指示第二格式的数据中的错误。

7. 发明授权

US07650372B2 Method and apparatus for varying-radix numeration system 失效
标题翻译：变数计算系统的方法和装置
公开(公告)号：US07650372B2
公开(公告)日：2010-01-19
申请号：US10676539
申请日：2003-09-30
申请人： Rongzhen Yang
发明人： Rongzhen Yang
IPC分类号： G06F15/00
CPC分类号： H03M7/12 , H03M7/18
摘要： A method and apparatus for a varying-radix numeration system is described. A method includes receiving a first sequence of values, determining a number of positions for a second sequence of values, and generating the second sequence of values, each value of the second sequence corresponding to a radix, the radix for each value of the second sequence varying over the second sequence in relation to an application value, the application value corresponding to a position in the second sequence and a sum of a set of values in the second sequence.
摘要翻译：描述了用于变化式数字系统的方法和装置。一种方法包括：接收第一序列值，确定第二序列值的位置数，并生成第二序列值，第二序列的每个值对应于基数，第二序列的每个值的基数相对于应用值改变第二序列，对应于第二序列中的位置的应用值和第二序列中的一组值的和。

8. 发明申请

US20060179090A1 System and method for converting binary to decimal 审中-公开
标题翻译：将二进制转换为十进制的系统和方法
公开(公告)号：US20060179090A1
公开(公告)日：2006-08-10
申请号：US11054232
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收二进制数，该二进制数包括一个或多个位组。累积和设为零。累加和是二进制编码十进制（BCD）格式。从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换成为5,1代码格式，产生临时总和。循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

9. 发明申请

US20060139189A1 GRAY CODE CONVERSION METHOD AND APPARATUS EMBODYING THE SAME 有权
标题翻译：灰色代码转换方法和装置实现
公开(公告)号：US20060139189A1
公开(公告)日：2006-06-29
申请号：US11020997
申请日：2004-12-23
申请人： Jonathan Sadowsky
发明人： Jonathan Sadowsky
IPC分类号： H03M7/12
CPC分类号： H03M7/16 , H03M7/12
摘要： A generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).
摘要翻译：广义格雷码转换器包括十进制到二进制到中间二进制转换器和中间二进制格雷码转换器。十进制到二进制到二进制转换器可操作以将以十进制二进制格式（十进制二进制序列）编码的电信号序列的序列转换为以中间二进制格式（中间序列）编码的电信号集合的序列，。连接到十进制到二进制到二进制转换器的中间二进制到格雷码转换器可操作以将中间序列转换成以格雷码二进制格式（格雷码序列）编码的一组电信号。

10. 发明申请

US20040059762A1 Method and apparatus for varying-radix numeration system 失效
标题翻译：变数计算系统的方法和装置
公开(公告)号：US20040059762A1
公开(公告)日：2004-03-25
申请号：US10676539
申请日：2003-10-01
发明人： Rongzhen Yang
IPC分类号： G06F015/00
CPC分类号： H03M7/12 , H03M7/18
摘要： A method and apparatus for a varying-radix numeration system is described. A method comprises receiving a first sequence of values, determining a number of positions for a second sequence of values, and generating the second sequence of values, each value of the second sequence corresponding to a radix, the radix for each value of the second sequence varying over the second sequence in relation to an application value, the application value corresponding to a position in the second sequence and a sum of a set of values in the second sequence.
摘要翻译：描述了用于变化式数字系统的方法和装置。一种方法包括：接收第一序列值，确定第二序列序列的位置数，以及产生所述第二序列值，所述第二序列的每个值对应于基数，所述第二序列的每个值的基数相对于应用值改变第二序列，对应于第二序列中的位置的应用值和第二序列中的一组值的和。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式