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1. 发明申请

US20060179090A1 System and method for converting binary to decimal 审中-公开
标题翻译：将二进制转换为十进制的系统和方法
公开(公告)号：US20060179090A1
公开(公告)日：2006-08-10
申请号：US11054232
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收二进制数，该二进制数包括一个或多个位组。累积和设为零。累加和是二进制编码十进制（BCD）格式。从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换成为5,1代码格式，产生临时总和。循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

2. 发明申请

US20050246507A1 Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data 有权
标题翻译：用于打包十进制数据的存储预对齐和EBCDIC，ASCII和unicode基本拉丁转换
公开(公告)号：US20050246507A1
公开(公告)日：2005-11-03
申请号：US10834637
申请日：2004-04-29
申请人： Fadi Busaba , Steven Carlough , Mark Check , Christopher Krygowski , John Rell , Frank Tanzi
发明人： Fadi Busaba , Steven Carlough , Mark Check , Christopher Krygowski , John Rell , Frank Tanzi
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F12/0886
摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.
摘要翻译：在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

3. 发明申请

US20070233773A1 MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
标题翻译：用于可变宽度的签名和不相关操作的模块化二进制多路复用器
公开(公告)号：US20070233773A1
公开(公告)日：2007-10-04
申请号：US11749224
申请日：2007-05-16
申请人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
发明人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
IPC分类号： G06F7/44
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.
摘要翻译：超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

4. 发明申请

US20060179102A1 System and method for performing decimal division 失效
公开(公告)号：US20060179102A1
公开(公告)日：2006-08-10
申请号：US11055221
申请日：2005-02-10
申请人： Steven Carlough , Paulomi Kadakia , Wen Li , Eric Schwarz
发明人： Steven Carlough , Paulomi Kadakia , Wen Li , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.

5. 发明申请

US20060179101A1 System and method for providing a decimal multiply algorithm using a double adder 失效
公开(公告)号：US20060179101A1
公开(公告)日：2006-08-10
申请号：US11054567
申请日：2005-02-09
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/496 , G06F2207/4911
摘要： A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

6. 发明申请

US20060179091A1 System and method for performing decimal to binary conversion 有权
标题翻译：用于执行十进制到二进制转换的系统和方法
公开(公告)号：US20060179091A1
公开(公告)日：2006-08-10
申请号：US11054233
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。运行总和和运行进位设置为零。对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

7. 发明申请

US20070214205A1 MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
标题翻译：用于可变宽度的签名和不相关操作的模块化二进制多路复用器
公开(公告)号：US20070214205A1
公开(公告)日：2007-09-13
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
发明人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

8. 发明申请

US20060179099A1 System and method for performing decimal floating point addition 失效
公开(公告)号：US20060179099A1
公开(公告)日：2006-08-10
申请号：US11055231
申请日：2005-02-10
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/4912 , G06F2207/4911
摘要： A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received. The operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. The applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder. The second concurrent calculation includes applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the second assumption results in a second result and includes utilizing the two cycle adder. The third concurrent calculation includes applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the third assumption results in a third result and includes utilizing the two cycle adder. A final result is selected from the first result, the second result and the third result.

9. 发明申请

US20050010631A1 Decimal multiplication using digit recoding 有权
标题翻译：使用数字重新编码的十进制乘法
公开(公告)号：US20050010631A1
公开(公告)日：2005-01-13
申请号：US10616556
申请日：2003-07-10
申请人： Steven Carlough , Eric Schwarz
发明人： Steven Carlough , Eric Schwarz
IPC分类号： G06F7/48 , G06F7/496 , G06F7/52
CPC分类号： G06F7/4824 , G06F7/496
摘要： A system and methodology for decimal multiplication in a microprocessor comprising: a recoder configured to recode decimal digits of a first operand to a corresponding set of {−5 to +5}. The recoder also configured to recode decimal digits of a second operand to a corresponding set of {−5 to +5}. The system also includes a multiplier array of digit multipliers, each digit multiplier configured to generate a partial product of a selected digit of a recoded first operand and a recoded second operand; and an adder array of digit adders, each adder configured to generate a sum of the partial products, wherein a least significant digit of the sum is shifted to a results register, and each adder includes carry feedback.
摘要翻译：一种微处理器中十进制乘法的系统和方法，包括：重新编码器，被配置为将第一操作数的十位数字重新编码为对应的{-5至+5}集合。编码器还配置为将第二操作数的十进制数字重新编码为相应的{-5到+5}集合。该系统还包括数字乘法器的乘法器阵列，每个数字乘法器被配置为生成重新编码的第一操作数的选定位数和重新编码的第二操作数的部分乘积; 和加法器数组加法器阵列，每个加法器被配置为产生部分乘积的和，其中该和的最低有效位被移位到结果寄存器，并且每个加法器包括进位反馈。

10. 发明申请

US20070061388A1 System and method for converting from scaled binary coded decimal into decimal floating point 有权
标题翻译：从缩放二进制编码十进制转换为十进制浮点的系统和方法
公开(公告)号：US20070061388A1
公开(公告)日：2007-03-15
申请号：US11227515
申请日：2005-09-15
申请人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
发明人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , H03M7/04
摘要： A system and method for converting from scaled binary coded decimal (SBCD) into decimal floating point (DFP). The system includes a mechanism for receiving one or more of an exponent part of a SBCD number and a coefficient part of the SBCD number. The system also includes at least one of a mechanism for performing coefficient compression on the coefficient part of the SBCD number to create a coefficient part of a DFP number and a mechanism for performing exponent insertion including inserting the exponent part of the SBCD number into an exponent part of the DFP number.
摘要翻译：从缩放二进制编码十进制（SBCD）转换为十进制浮点（DFP）的系统和方法。该系统包括用于接收SBCD号的指数部分和SBCD号的系数部分中的一个或多个的机构。该系统还包括用于对SBCD号码的系数部分执行系数压缩以创建DFP号码的系数部分的机制和用于执行指数插入的机制中的至少一个，包括将SBCD号码的指数部分插入指数 DFP编号的一部分。

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