会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • CODED SIGNAL REPRODUCTION APPARATUS
    • 编码信号再现装置
    • US20090257735A1
    • 2009-10-15
    • US12486279
    • 2009-06-17
    • Ryoji YAMAGUCHIEiji Miyagoshi
    • Ryoji YAMAGUCHIEiji Miyagoshi
    • H04N5/91
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter 2s13 is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit 2s3, is detected, the start code prefix detection unit 2s3 detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter 2s13 outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer 2s9, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating the packet boundary are output to the decoding buffer 2s9. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit 2s4 is simplified, and thereby the hardware scale is reduced, resulting-in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器2s13,并且当检测到与由起始码前缀检测单元2s3检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元2s3检测 检测到的预定码序列的残差部分('00','00','01','E0'),以检测('00','00','00')的模式,格式器2s13输出一个 ('00')。 在分组的边界被定义之后,在未传送到解码缓冲器2s9的数据中,对应于指示分组的代码序列('00','00','01','E0')之外的代码序列的数据 边界输出到解码缓冲器2s9。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路2s4的控制,从而降低了硬件规模,从而导致用于再现数字代码序列的便宜的装置。
    • 3. 发明授权
    • Video encoding apparatus and method
    • 视频编码装置及方法
    • US6137838A
    • 2000-10-24
    • US7069
    • 1998-01-14
    • Eiji MiyagoshiAkihiro Watabe
    • Eiji MiyagoshiAkihiro Watabe
    • H04N7/26H04N7/50
    • H04N19/423H04N19/124H04N19/152H04N19/176H04N19/61H04N19/91H04N19/149H04N19/15
    • The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.
    • 本发明提供一种包括用于对输入视频数据执行视频处理的视频处理器的视频编码装置,用于对经处理的(量化的)视频数据执行可变长度编码并提供编码数据和生成的比特量的可变长度编码器, 用于存储作为比特流输出的编码数据的DRAM,用于基于从预先预定的设定比特量中减去所生成的比特量而得到的值,计算从DRAM读取的周期的比特流输出电路 并且用于在计算的周期中输出比特流作为输出视频数据,以及用于控制视频处理器,可变长度编码器,DRAM和比特流输出电路的操作的仲裁器。
    • 4. 发明授权
    • Coded signal reproduction apparatus
    • 编码信号再生装置
    • US08649662B2
    • 2014-02-11
    • US12486279
    • 2009-06-17
    • Ryoji YamaguchiEiji Miyagoshi
    • Ryoji YamaguchiEiji Miyagoshi
    • H04N9/80H04N5/93
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter 2s13 is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit 2s3, is detected, the start code prefix detection unit 2s3 detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter 2s13 outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer 2s9, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating the packet boundary are output to the decoding buffer 2s9. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit 2s4 is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器2s13,并且当检测到与由起始码前缀检测单元2s3检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元2s3检测 检测到的预定码序列的残差部分('00','00','01','E0'),以检测('00','00','00')的模式,格式器2s13输出一个 ('00')。 在分组的边界被定义之后,在未传送到解码缓冲器2s9的数据中,对应于指示分组的代码序列('00','00','01','E0')之外的代码序列的数据 边界输出到解码缓冲器2s9。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路2s4的控制,从而降低了硬件规模,导致了用于再现数字代码序列的便宜的装置。
    • 8. 发明授权
    • Image processor
    • 图像处理器
    • US06356317B1
    • 2002-03-12
    • US08911919
    • 1997-08-15
    • Akihiro WatabeEiji Miyagoshi
    • Akihiro WatabeEiji Miyagoshi
    • H04N964
    • H04N19/427H04N19/423H04N19/61
    • A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.
    • 提供了一个帧存储器,其具有五个场,每个场具有N个时隙,以及三个附加时隙。 每个插槽具有存储8个图像行的存储容量。 五个场中的四个场用于存储运动补偿参考帧。 剩余的一个场和三个附加时隙用于B图像交错转换。 设置在控制单元中的是时隙控制存储器,写槽指针和读槽指针。 对于图像输出单元,以正确的时隙顺序从帧存储器获取信息,在执行写入操作时更新时隙控制存储器的内容,以便通过比特流分析单元将信息输入到帧存储器中。
    • 10. 发明授权
    • Apparatus for reproduction of encoded signal
    • 用于再现编码信号的装置
    • US07809246B1
    • 2010-10-05
    • US09380187
    • 1998-12-28
    • Ryoji YamaguchiEiji Miyagoshi
    • Ryoji YamaguchiEiji Miyagoshi
    • H04N7/26
    • H04N21/4347H04J3/0608H04N19/70H04N21/236H04N21/4305H04N21/434
    • A formatter is provided and, when a code sequence which matches a part (‘00’) of the head of a predetermined code sequence detected by a start code prefix detection unit, is detected, the start code prefix detection unit detects the residual part (‘00’, ‘00’, ‘01’, ‘E0’) of the detected predetermined code sequence to detect a pattern of (‘00’, ‘00’, ‘00’), and the formatter outputs one (‘00’). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer, data corresponding to code sequences other than the code sequence (‘00’, ‘00’, ‘01’, ‘E0’) indicating that the packet boundary are output to the decoding buffer. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.
    • 提供格式化器,并且当检测到与由起始码前缀检测单元检测到的预定码序列的头部的部分('00')匹配的码序列时,起始码前缀检测单元检测残留部分 '00','00','00','01','E0'),以检测('00','00','00')的模式,并且格式化器输出一个('00' )。 在定义分组边界之后,在不传送到解码缓冲器的数据中,对应于代码序列('00','00','01','E0')之外的代码序列的数据指示分组 边界输出到解码缓冲器。 因此,当分离编码和复用的信号时,简化了输入缓冲器读取控制电路的控制,从而降低了硬件规模,导致了用于再现数字代码序列的廉价的装置。