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    • 1. 发明授权
    • Method for reducing tuning etch in a clock-forwarded interface
    • 降低时钟转发接口中调谐蚀刻的方法
    • US06754838B2
    • 2004-06-22
    • US09770589
    • 2001-01-26
    • Douglas J. BurnsRoger Dame
    • Douglas J. BurnsRoger Dame
    • G06F112
    • H04L7/0008
    • A clock forwarding scheme for use in a system comprising a plurality of communications links, each link configured to transmit data packets and a forwarded clock from a transmitting device to a receiving device. The required delay in the forwarded clock signal is generated at the transmitting device by adding tuning etch to the signal path for the forwarded clock signal prior to transmission of the forwarded clock signal and data packets. The source device preferably has at least two clock output pins to deliver two synchronous clock signals off the device and at least two clock input pins to receive the clock signals. One of the two clock signals is delayed with respect to the other via a longer conduction path. The delayed clock signal is used to trigger logic to transmit the forwarded clock signal. The undelayed clock signal is used to trigger logic to transmit data bits.
    • 一种在包括多个通信链路的系统中使用的时钟转发方案,每个链路被配置为从发送设备向接收设备发送数据分组和转发时钟。 通过在转发的时钟信号和数据分组的发送之前,通过在转发的时钟信号的信号路径上添加调谐蚀刻,在发送设备处产生所需的延迟。 源装置优选地具有至少两个时钟输出引脚以从装置和至少两个时钟输入引脚输出两个同步时钟信号以接收时钟信号。 两个时钟信号中的一个相对于另一个通过较长的传导路径被延迟。 延迟时钟信号用于触发发送转发的时钟信号的逻辑。 未延时的时钟信号用于触发发送数据位的逻辑。