专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070085128A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070085128A1
公开(公告)日：2007-04-19
申请号：US11608672
申请日：2006-12-08
申请人： Dong-Sauk KIM , Ho-Seok Lee , Byung-Jun Park , Il-Young Kwon , Jong-Min Lee , Hyeong-Soo Kim , Jin-Woong Kim , Hyung-Bok Choi , Dong-Woo Shin
发明人： Dong-Sauk KIM , Ho-Seok Lee , Byung-Jun Park , Il-Young Kwon , Jong-Min Lee , Hyeong-Soo Kim , Jin-Woong Kim , Hyung-Bok Choi , Dong-Woo Shin
IPC分类号： H01L29/76
CPC分类号： H01L27/10855 , H01L27/0207 , H01L27/10814
摘要： Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.
摘要翻译：公开了半导体装置及其制造方法，其能够通过扩大有效的电容器面积来形成下部电极并且通过扩大电容器的足够的电容来防止由倾斜或提升现象引起的较短的下部电极。本发明的半导体器件包括：以有序的间隔距离设置的多个电容器插头; 以及多个用于电容器的下电极，并且以与电容器插头分别连接的有序分隔距离设置。

2. 发明申请

US20050018525A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050018525A1
公开(公告)日：2005-01-27
申请号：US10625277
申请日：2003-07-23
申请人： Dong-Sauk Kim , Ho-Seok Lee , Byung-Jun Park , Il-Young Kwon , Jong-Min Lee , Hyeong-Soo Kim , Jin-Woong Kim , Hyung-Bok Choi , Dong-Woo Shin
发明人： Dong-Sauk Kim , Ho-Seok Lee , Byung-Jun Park , Il-Young Kwon , Jong-Min Lee , Hyeong-Soo Kim , Jin-Woong Kim , Hyung-Bok Choi , Dong-Woo Shin
IPC分类号： H01L21/8242 , G11C8/02 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10855 , H01L27/0207 , H01L27/10814
摘要： Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.
摘要翻译：公开了半导体装置及其制造方法，其能够通过扩大有效的电容器面积来形成下部电极并且通过扩大电容器的足够的电容来防止由倾斜或提升现象引起的较短的下部电极。本发明的半导体器件包括：以有序的间隔距离设置的多个电容器插头; 以及多个用于电容器的下电极，并且以与电容器插头分别连接的有序分隔距离设置。

3. 发明申请

US20110133283A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20110133283A1
公开(公告)日：2011-06-09
申请号：US12649637
申请日：2009-12-30
申请人： Jeong Hoon PARK , Dong Sauk KIM
发明人： Jeong Hoon PARK , Dong Sauk KIM
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L21/823456 , H01L27/10876 , H01L27/10894 , H01L29/4236
摘要： A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.
摘要翻译：半导体器件包括其中形成单元区域和外围区域之间的高度差的结构，使得单元区域的掩埋栅极结构的高度与周边区域的栅极高度相等，由此位线可以更容易地在单元区域中形成存储节点接触，并且可以减小寄生电容。半导体器件包括包含埋在衬底中的栅极的单元区域和与单元区域相邻的周边区域，其中生成单元表面和外围区域表面之间的台阶高度。

4. 发明申请

US20070148964A1 Method for forming contact hole in semiconductor device 有权
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US20070148964A1
公开(公告)日：2007-06-28
申请号：US11448714
申请日：2006-06-08
申请人： Dong-Yeol Lee , Dong-Goo Choi , Dong-Sauk Kim
发明人： Dong-Yeol Lee , Dong-Goo Choi , Dong-Sauk Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/76805 , H01L21/76829
摘要： A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including an etch stop layer over the substrate, forming a contact mask over the inter-layer insulation layer, performing a first etching process to etch a first portion of the inter-layer insulation layer above the etch stop layer, using the contact mask as an etch mask, and performing a second etching process to etch the etch stop layer, a second portion of the inter-layer insulation layer below the etch stop layer, and the bit line hard mask to form a contact hole exposing a portion of the bit line.
摘要翻译：一种用于在半导体器件中形成接触孔的方法包括在衬底上形成栅极线，通过在衬底上依次形成位线和位线硬掩模形成位线图案，形成层间绝缘层，该层间绝缘层具有包括在衬底上的蚀刻停止层的多层结构，在层间绝缘层上形成接触掩模，执行第一蚀刻工艺以蚀刻蚀刻停止层上方的层间绝缘层的第一部分，使用所述接触掩模作为蚀刻掩模，以及执行蚀刻所述蚀刻停止层的第二蚀刻工艺，所述蚀刻停止层下面的所述层间绝缘层的第二部分和所述位线硬掩模以形成暴露于位线的一部分。

5. 发明申请

US20070128795A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20070128795A1
公开(公告)日：2007-06-07
申请号：US11673353
申请日：2007-02-09
申请人： Seung-Bum Kim , Dong-sauk Kim , Jung-Taik Cheong
发明人： Seung-Bum Kim , Dong-sauk Kim , Jung-Taik Cheong
IPC分类号： H01L21/8242
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

6. 发明授权

US07226829B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07226829B2
公开(公告)日：2007-06-05
申请号：US10749533
申请日：2003-12-30
申请人： Chang-Youn Hwang , Dong-Sauk Kim , Jin-Ki Jung
发明人： Chang-Youn Hwang , Dong-Sauk Kim , Jin-Ki Jung
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.
摘要翻译：本发明涉及一种用于形成半导体器件的存储节点的方法。该方法包括以下步骤：（a）形成多个位线图案，每个位线图案包括依次层叠在基板结构的表面上的导线和硬掩模; （b）沿着包含位线图形的轮廓依次形成第一阻挡层和第一层间绝缘层，直到填充位线图形之间的空间; （c）蚀刻第一层间绝缘层，直到第一层间绝缘层的部分部分保留在位线图案之间的每个空间上; （d）在第一层间绝缘层和第一阻挡层上形成第二阻挡层; 和（e）蚀刻第一和第二阻挡层和剩余的第一层间绝缘层以暴露位于位线图案之间的衬底结构的表面。

7. 发明授权

US06838369B2 Method for forming contact hole of semiconductor device 有权
标题翻译：形成半导体器件接触孔的方法
公开(公告)号：US06838369B2
公开(公告)日：2005-01-04
申请号：US10608116
申请日：2003-06-30
申请人： Ho Seok Lee , Dong Sauk Kim , Jin Woong Kim
发明人： Ho Seok Lee , Dong Sauk Kim , Jin Woong Kim
IPC分类号： H01L21/28 , H01L21/306 , H01L21/311 , H01L21/44 , H01L21/4763 , H01L21/60
CPC分类号： H01L21/02063 , H01L21/02052 , H01L21/31116 , H01L21/76897 , Y10S438/902 , Y10S438/906 , Y10S438/963
摘要： A method for forming a contact hole of a semiconductor device, wherein a polymer residual on a bottom surface of the contact hole is treated with plasma of mixture gas containing oxygen to convert the polymer residual into a pure silicon oxide film free of carbon and fluorine for easy removal in a subsequent washing process is disclosed. The method comprises (a) sequentially forming a capping layer and a planarized interlayer insulating film on a semiconductor substrate having a predetermined lower structure; (b) selectively etching the interlayer insulating film to expose a predetermined region of the capping layer; (c) removing the exposed capping layer; (d) subjecting the resulting structure to a plasma treatment using a mixture gas containing oxygen; and (e) performing a cleaning process.

8. 发明授权

US5668064A Method of forming a tungsten plug in a semiconductor device 失效
标题翻译：在半导体器件中形成钨插塞的方法
公开(公告)号：US5668064A
公开(公告)日：1997-09-16
申请号：US606305
申请日：1996-02-23
申请人： Sang Hoon Park , Dong Sauk Kim , Ju Il Lee
发明人： Sang Hoon Park , Dong Sauk Kim , Ju Il Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L21/60
CPC分类号： H01L21/76838 , H01L23/5226 , H01L2924/0002
摘要： The present invention discloses a method of forming a tungsten plug within a via hole in which it sequentially forms a barrier metal layer and a tungsten layer on a insulating film including the via hole, forms a photoresist pattern of which size is enough to cover the via hole on the tungsten layer in the upper side of the via hole, etching the tungsten layer by sequentially performing an isotropic etching process and an anisotropic etching process using the photoresist pattern as an etching mask and, after the photoresist pattern is removed, etching the projections of the tungsten layer by performing the anisotropic etching process.
摘要翻译：本发明公开了一种在通孔内形成钨插塞的方法，其中它依次在包括通孔的绝缘膜上形成阻挡金属层和钨层，形成尺寸足以覆盖通孔的光致抗蚀剂图案在通孔的上侧的钨层上的孔，通过依次进行各向同性蚀刻工艺和使用光致抗蚀剂图案作为蚀刻掩模的各向异性蚀刻工艺蚀刻钨层，并且在除去光致抗蚀剂图案之后，蚀刻突起通过进行各向异性蚀刻处理。

9. 发明授权

US07521347B2 Method for forming contact hole in semiconductor device 有权
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US07521347B2
公开(公告)日：2009-04-21
申请号：US11448714
申请日：2006-06-08
申请人： Dong-Yeol Lee , Dong-Goo Choi , Dong-Sauk Kim
发明人： Dong-Yeol Lee , Dong-Goo Choi , Dong-Sauk Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/76805 , H01L21/76829
摘要： A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including an etch stop layer over the substrate, forming a contact mask over the inter-layer insulation layer, performing a first etching process to etch a first portion of the inter-layer insulation layer above the etch stop layer, using the contact mask as an etch mask, and performing a second etching process to etch the etch stop layer, a second portion of the inter-layer insulation layer below the etch stop layer, and the bit line hard mask to form a contact hole exposing a portion of the bit line.
摘要翻译：一种用于在半导体器件中形成接触孔的方法包括在衬底上形成栅极线，通过在衬底上依次形成位线和位线硬掩模形成位线图案，形成层间绝缘层，该层间绝缘层具有包括在衬底上的蚀刻停止层的多层结构，在层间绝缘层上形成接触掩模，执行第一蚀刻工艺以蚀刻蚀刻停止层上方的层间绝缘层的第一部分，使用所述接触掩模作为蚀刻掩模，以及执行蚀刻所述蚀刻停止层的第二蚀刻工艺，所述蚀刻停止层下面的所述层间绝缘层的第二部分和所述位线硬掩模以形成暴露于位线的一部分。

10. 发明授权

US07518175B2 Semiconductor memory device and method for fabricating the same 有权
公开(公告)号：US07518175B2
公开(公告)日：2009-04-14
申请号：US11673344
申请日：2007-02-09
申请人： Seung-Bum Kim , Dong-sauk Kim , Jung-Taik Cheong
发明人： Seung-Bum Kim , Dong-sauk Kim , Jung-Taik Cheong
IPC分类号： H01L27/108
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式