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1. 发明申请

US20140129808A1 MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开
标题翻译：多核处理器的不对称计算元素之间的迁移任务
公开(公告)号：US20140129808A1
公开(公告)日：2014-05-08
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。描述和要求保护其他实施例。

2. 发明授权

US08479208B2 System partitioning to present software as platform level functionality including mode logic to maintain and enforce partitioning in first and configure partitioning in second mode 有权
标题翻译：系统分区将软件呈现为平台级功能，包括在第一种模式下首先维护和强制划分并配置分区的模式逻辑
公开(公告)号：US08479208B2
公开(公告)日：2013-07-02
申请号：US11694276
申请日：2007-03-30
申请人： Stephen J. Tolopka , David A. Koufaty , John I. Garney , Yasser Rasheed , Ulhas Warrier , Matthew Hoekstra
发明人： Stephen J. Tolopka , David A. Koufaty , John I. Garney , Yasser Rasheed , Ulhas Warrier , Matthew Hoekstra
IPC分类号： G06F9/50
CPC分类号： G06F9/5077 , G06F8/65 , G06F9/45533 , G06F9/45558 , G06F12/1491 , G06F21/74
摘要： Embodiments of apparatuses, methods for partitioning systems, and partitionable and partitioned systems are disclosed. In one embodiment, a system includes processors and a partition manager. The partition manager is to allocate a subset of the processors to a first partition and another subset of the processors to a second partition. The first partition is to execute first operating system level software and the second partition is to execute second operating system level software. The first operating system level software is to manage the processors in the first partition as resources individually accessible to the first operating system level software, and the second operating system level software is to manage the processors in the second partition as resources individually accessible to the second operating system level software. The partition manager is also to present the second partition, including the second operating system level software, to the first operating system level software as platform level functionality embedded in the system.
摘要翻译：公开了装置的实施例，分区系统的方法以及可分割和分区的系统。在一个实施例中，系统包括处理器和分区管理器。分区管理器将处理器的子集分配给第一分区，另一个处理器子集分配给第二分区。第一个分区是执行第一个操作系统级软件，第二个分区是执行第二个操作系统级软件。第一操作系统级软件是将第一分区中的处理器作为第一操作系统级软件单独访问的资源进行管理，而第二操作系统级软件则将第二分区中的处理器作为第二分区可访问的资源进行管理操作系统级软件。分区管理器还将第二分区（包括第二操作系统级软件）呈现给第一操作系统级软件，作为嵌入系统中的平台级功能。

3. 发明授权

US07516313B2 Predicting contention in a processor 失效
标题翻译：预测处理器中的争用
公开(公告)号：US07516313B2
公开(公告)日：2009-04-07
申请号：US11027392
申请日：2004-12-29
申请人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
IPC分类号： G06F13/376 , G06F9/38 , G06F13/18
CPC分类号： G06F9/3851 , G06F9/526
摘要： In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。在一个实施例中，如果没有预测到争用，则可以优化操作。描述和要求保护其他实施例。

4. 发明授权

US10185566B2 Migrating tasks between asymmetric computing elements of a multi-core processor 有权
公开(公告)号：US10185566B2
公开(公告)日：2019-01-22
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30 , G06F9/48 , G06F9/50
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

5. 发明申请

US20190004990A1 TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT 审中-公开
公开(公告)号：US20190004990A1
公开(公告)日：2019-01-03
申请号：US15640463
申请日：2017-07-01
申请人： STEPHEN R. VAN DOREN , RAJESH M. SANKARAN , DAVID A. KOUFATY , RAMACHARAN SUNDARARAMAN , ISHWAR AGARWAL
发明人： STEPHEN R. VAN DOREN , RAJESH M. SANKARAN , DAVID A. KOUFATY , RAMACHARAN SUNDARARAMAN , ISHWAR AGARWAL
IPC分类号： G06F13/42 , G06F13/14
摘要： Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

6. 发明申请

US20140189299A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189299A1
公开(公告)日：2014-07-03
申请号：US13730565
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/38
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

7. 发明申请

US20130290978A1 System Partitioning To Present Software As Platform Level Functionality 审中-公开
标题翻译：系统分区将软件呈现为平台级功能
公开(公告)号：US20130290978A1
公开(公告)日：2013-10-31
申请号：US13918277
申请日：2013-06-14
申请人： Stephen J. Tolopka , David A. Koufaty , John I. Garney , Yasser Rasheed , Ulhas Warrier , Matthew Hoekstra
发明人： Stephen J. Tolopka , David A. Koufaty , John I. Garney , Yasser Rasheed , Ulhas Warrier , Matthew Hoekstra
IPC分类号： G06F9/50
CPC分类号： G06F9/5077 , G06F8/65 , G06F9/45533 , G06F9/45558 , G06F12/1491 , G06F21/74
摘要： Embodiments of apparatuses, methods for partitioning systems, and partitionable and partitioned systems are disclosed. In one embodiment, a system includes processors and a partition manager. The partition manager is to allocate a subset of the processors to a first partition and another subset of the processors to a second partition. The first partition is to execute first operating system level software and the second partition is to execute second operating system level software. The first operating system level software is to manage the processors in the first partition as resources individually accessible to the first operating system level software, and the second operating system level software is to manage the processors in the second partition as resources individually accessible to the second operating system level software. The partition manager is also to present the second partition, including the second operating system level software, to the first operating system level software as platform level functionality embedded in the system.
摘要翻译：公开了装置的实施例，分区系统的方法以及可分割和分区的系统。在一个实施例中，系统包括处理器和分区管理器。分区管理器将处理器的子集分配给第一分区，另一个处理器子集分配给第二分区。第一个分区是执行第一个操作系统级软件，第二个分区是执行第二个操作系统级软件。第一操作系统级软件是将第一分区中的处理器作为第一操作系统级软件单独访问的资源进行管理，而第二操作系统级软件则将第二分区中的处理器作为第二分区可访问的资源进行管理操作系统级软件。分区管理器还将第二分区（包括第二操作系统级软件）呈现给第一操作系统级软件，作为嵌入系统中的平台级功能。

8. 发明授权

US07363474B2 Method and apparatus for suspending execution of a thread until a specified memory access occurs 有权
标题翻译：用于挂起执行线程的方法和装置，直到发生指定的存储器访问
公开(公告)号：US07363474B2
公开(公告)日：2008-04-22
申请号：US10039579
申请日：2001-12-31
申请人： Dion Rodgers , Deborah T. Marr , David L. Hill , Shiv Kaushik , James B. Crossland , David A. Koufaty
发明人： Dion Rodgers , Deborah T. Marr , David L. Hill , Shiv Kaushik , James B. Crossland , David A. Koufaty
IPC分类号： G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3009 , G06F9/30079 , G06F9/3851 , G06F9/4812 , G06F9/4843
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.
摘要翻译：暂停执行线程直到发生指定的内存访问的技术。在一个实施例中，处理器包括能够执行多个线程的多个执行单元。第一个线程包括指定监视器地址的指令。挂起逻辑挂起执行第一个线程，并且监视器导致第一个线程的恢复以响应对指定的监视器地址的访问。

9. 发明申请

US20170249260A1 SYSTEM FOR ADDRESS MAPPING AND TRANSLATION PROTECTION 审中-公开
公开(公告)号：US20170249260A1
公开(公告)日：2017-08-31
申请号：US15088739
申请日：2016-04-01
申请人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
发明人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
IPC分类号： G06F12/14 , G06F12/10 , G06F21/62 , G06F3/06
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

10. 发明申请

US20140281457A1 METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法
公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译：描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

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