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1. 发明申请

US20140189299A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189299A1
公开(公告)日：2014-07-03
申请号：US13730565
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/38
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

2. 发明申请

US20140189704A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189704A1
公开(公告)日：2014-07-03
申请号：US13730539
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F9/45533 , G06F9/5077 , G06F9/5094 , G06F15/80 , Y02D10/22
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行从第一组或第二组物理处理器到第一虚拟处理器。

3. 发明申请

US20140189297A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189297A1
公开(公告)日：2014-07-03
申请号：US13730491
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Gaurav Khanna , Russell J. Fenger , Bryant E. Bigbee , Andrew D. Henroid
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Gaurav Khanna , Russell J. Fenger , Bryant E. Bigbee , Andrew D. Henroid
IPC分类号： G06F15/76
CPC分类号： G06F9/45558 , G06F9/3885 , G06F9/5077 , G06F2009/4557
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。

4. 发明申请

US20140189301A1 HIGH DYNAMIC RANGE SOFTWARE-TRANSPARENT HETEROGENEOUS COMPUTING ELEMENT PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：高动态范围软件 - 透明异构计算元件处理器，方法和系统
公开(公告)号：US20140189301A1
公开(公告)日：2014-07-03
申请号：US13730800
申请日：2012-12-28
申请人： Eugene Gorbatov , Alon Naveh , Inder M. Sodhi , Ganapati N. Srinivasa , Eliezer Weissmann , Guarav Khanna , Mishali Naik , Russell J. Fenger , Andrew D. Henroid , Dheeraj R. Subbareddy , David A. Koufaty , Paolo Narvaez
发明人： Eugene Gorbatov , Alon Naveh , Inder M. Sodhi , Ganapati N. Srinivasa , Eliezer Weissmann , Guarav Khanna , Mishali Naik , Russell J. Fenger , Andrew D. Henroid , Dheeraj R. Subbareddy , David A. Koufaty , Paolo Narvaez
IPC分类号： G06F15/80
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/22
摘要： A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
摘要翻译：一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元件迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下方式确定是否允许基于评估性能好处。可用的能源和热力预算评估逻辑是评估可用的能源和热力预算，并确定如果迁移符合可用能源和热预算，则允许迁移。工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

5. 发明授权

US09081707B2 Apparatus and method for tracking TLB flushes on a per thread basis 有权
标题翻译：用于跟踪TLB在每个线程上刷新的装置和方法
公开(公告)号：US09081707B2
公开(公告)日：2015-07-14
申请号：US13730906
申请日：2012-12-29
申请人： Shaun M. Conrad , Russell J. Fenger , Gaurav Khanna , Rahul Seth , James B. Crossland , Anil Aggarwal
发明人： Shaun M. Conrad , Russell J. Fenger , Gaurav Khanna , Rahul Seth , James B. Crossland , Anil Aggarwal
IPC分类号： G06F12/02 , G06F12/10 , G06F1/32
CPC分类号： G06F12/1027 , G06F1/3206 , G06F2212/683 , Y02D10/13
摘要： A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.
摘要翻译：描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。

6. 发明申请

US20160077576A1 TECHNOLOGIES FOR COLLABORATIVE HARDWARE AND SOFTWARE SCENARIO-BASED POWER MANAGEMENT 审中-公开
标题翻译：协同硬件和软件基于场景的电源管理技术
公开(公告)号：US20160077576A1
公开(公告)日：2016-03-17
申请号：US14488805
申请日：2014-09-17
申请人： Abhinav R. Karhu , Guarav Khanna , Russell J. Fenger
发明人： Abhinav R. Karhu , Guarav Khanna , Russell J. Fenger
IPC分类号： G06F1/32
CPC分类号： G06F1/3246 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Technologies for collaborative hardware-software power management include a computing device having a processor that supports a low-power idle state. The low-power idle state may be connected standby or a low-power audio playback state. The computing device detects a present usage scenario and determines whether the usage scenario qualifies for a power boost. Qualifying usage scenarios may include low-power audio playback, screen-on interactive use, and I/O-bound workloads. For qualifying usage scenarios, the computing device applies a boosted power management policy that increases power consumption and performance compared to a default power management policy. The default power management policy may base performance and power consumption on recent processor utilization. The computing device may generate one or more hardware hints to increase performance and power consumption, such as increasing the processor p-state or setting the value of an energy performance bias register. Other embodiments are described and claimed.
摘要翻译：用于协作硬件 - 软件电源管理的技术包括具有支持低功率空闲状态的处理器的计算设备。低功率空闲状态可以连接待机或低功率音频播放状态。计算设备检测当前使用情景并确定使用情景是否符合功率提升。合格使用场景可能包括低功耗音频播放，屏幕交互式使用和I / O绑定工作负载。对于符合条件的使用情况，计算设备应用升级的电源管理策略，与默认电源管理策略相比，可提高功耗和性能。默认的电源管理策略可以基于最近处理器利用率的性能和功耗。计算设备可以生成一个或多个硬件提示以增加性能和功耗，例如增加处理器p状态或设置能量性能偏置寄存器的值。描述和要求保护其他实施例。

7. 发明授权

US08898494B2 Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached 有权
标题翻译：处理核心，图形核心和集成电路总线之间的功率预算，达到极限
公开(公告)号：US08898494B2
公开(公告)日：2014-11-25
申请号：US13398641
申请日：2012-02-16
申请人： Travis T. Schluessler , Russell J. Fenger
发明人： Travis T. Schluessler , Russell J. Fenger
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
摘要翻译：这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。

8. 发明授权

US08813080B2 System and method to optimize OS scheduling decisions for power savings based on temporal characteristics of the scheduled entity and system workload 有权
标题翻译：基于调度实体和系统工作负载的时间特征优化用于节电的OS调度决策的系统和方法
公开(公告)号：US08813080B2
公开(公告)日：2014-08-19
申请号：US11770376
申请日：2007-06-28
申请人： Russell J. Fenger , Leena K. Puthiyedath
发明人： Russell J. Fenger , Leena K. Puthiyedath
IPC分类号： G06F9/46 , G06F1/00 , G06F9/30
CPC分类号： G06F9/4893 , Y02D10/24
摘要： In some embodiments, the invention involves a system and method to enhance an operating system's ability to schedule ready threads, specifically to select a logical processor on which to run the ready thread, based on platform policy. Platform policy may be performance-centric, power-centric, or a balance of the two. Embodiments of the present invention use temporal characteristics of the system utilization, or workload, and/or temporal characteristics of the ready thread in choosing a logical processor. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明涉及一种系统和方法，用于增强操作系统调度就绪线程的能力，特别是基于平台策略来选择在其上运行就绪线程的逻辑处理器。平台策略可能是以绩效为中心，以权力为中心，或两者平衡。在选择逻辑处理器时，本发明的实施例使用系统利用率，工作负载的时间特性和/或就绪线程的时间特性。描述和要求保护其他实施例。

9. 发明申请

US20090089598A1 SYSTEM AND METHOD FOR SELECTING OPTIMAL PROCESSOR PERFORMANCE LEVELS BY USING PROCESSOR HARDWARE FEEDBACK MECHANISMS 有权
标题翻译：使用处理器硬件反馈机制选择最佳处理器性能水平的系统和方法
公开(公告)号：US20090089598A1
公开(公告)日：2009-04-02
申请号：US11864800
申请日：2007-09-28
申请人： Russell J. Fenger , Anil Aggarwal , Shiv Kaushik
发明人： Russell J. Fenger , Anil Aggarwal , Shiv Kaushik
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior.
摘要翻译：本发明的一个实施例是涉及使用硬件反馈的自适应功率管理以选择最佳处理器频率并降低功率/功率的系统和方法。在至少一个实施例中，本发明旨在基于硬件反馈和处理器失速行为来优化处理器频率和功率/瓦特使用。

10. 发明申请

US20090007120A1 SYSTEM AND METHOD TO OPTIMIZE OS SCHEDULING DECISIONS FOR POWER SAVINGS BASED ON TEMPORAL CHARACTERISTICS OF THE SCHEDULED ENTITY AND SYSTEM WORKLOAD 有权
标题翻译：基于调度实体的时间特征和系统工作负载优化功率节省的操作系统调度决策的系统和方法
公开(公告)号：US20090007120A1
公开(公告)日：2009-01-01
申请号：US11770376
申请日：2007-06-28
申请人： Russell J. Fenger , Leana K. Puthiyedath
发明人： Russell J. Fenger , Leana K. Puthiyedath
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： In some embodiments, the invention involves a system and method to enhance an operating system's ability to schedule ready threads, specifically to select a logical processor on which to run the ready thread, based on platform policy. Platform policy may be performance-centric, power-centric, or a balance of the two. Embodiments of the present invention use temporal characteristics of the system utilization, or workload, and/or temporal characteristics of the ready thread in choosing a logical processor. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明涉及一种系统和方法，用于增强操作系统调度就绪线程的能力，特别是基于平台策略来选择在其上运行就绪线程的逻辑处理器。平台策略可能是以绩效为中心，以权力为中心，或两者平衡。在选择逻辑处理器时，本发明的实施例使用系统利用率，工作负载的时间特性和/或就绪线程的时间特性。描述和要求保护其他实施例。

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