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1. 发明授权

US08605719B2 Circuit with network of message distributor circuits 有权
标题翻译：电路与消息分配器电路网络
公开(公告)号：US08605719B2
公开(公告)日：2013-12-10
申请号：US12452643
申请日：2008-07-07
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： H04L12/50 , H04Q11/00 , G06F3/00 , G06F5/00 , G06F13/00 , H04L12/56 , G06F15/17 , G06F15/173 , G06F15/163
CPC分类号： H04L49/15 , G06F9/5027 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173 , G06F15/17356 , G06F15/17393 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/10 , H04L49/101 , H04L49/1507 , H04L49/25 , H04L49/506
摘要： Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.
摘要翻译：源电路（10）产生可以由多个处理电路（14）中的任何一个处理的消息。在源电路和处理电路（14）之间提供分配器电路网络。网络中的分配器电路的本地决定决定了消息将被路由到哪个处理电路的每个消息。消息提供给至少两个并行分配器电路。这些分配器电路（12a）基于其他分配器电路（12b）中的各个的当前可用性从网络中的其它分配器电路（12b）中进行选择。根据数据处理电路（14）的当前可用性，各个消息依次由所选择的另外的分配器电路（12b）选择的路径从所选择的另外的分配器电路（12b）转发到数据处理电路（14），以及 /或后续的分配器电路（12c）。

2. 发明授权

US08489825B2 Method of storing data, method of loading data and signal processor 有权
标题翻译：存储数据的方法，数据加载方法和信号处理器
公开(公告)号：US08489825B2
公开(公告)日：2013-07-16
申请号：US12450819
申请日：2008-04-11
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3885
摘要： A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, —storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).
摘要翻译：描述了一种用于将具有从寄存器文件（RF）到n存储器（M）的n位大小的处理数据元素（D1，...，D8）的向量存储的方法。存储器被布置用于将存储数据元素的矢量存储在具有m位大小的位置（M1，... M5）中，其中m> n。该方法包括以下步骤：在存储在相互后继的寄存器元件中的向量中交换处理数据元素之间的位（S2），产生修改后的数据元素（DmI，...，Dm8），混洗（S3）在所得到的向量中的k个后续比特的组，将修改的数据元素的所得混洗向量（S4）存储（S4）作为存储器（M）中的存储数据元素的向量。

3. 发明申请

US20110044328A1 CIRCUIT WITH NETWORK OF MESSAGE DISTRIBUTOR CIRCUITS 有权
标题翻译：具有消息分发电路网络的电路
公开(公告)号：US20110044328A1
公开(公告)日：2011-02-24
申请号：US12452643
申请日：2008-07-07
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： H04L12/50
CPC分类号： H04L49/15 , G06F9/5027 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173 , G06F15/17356 , G06F15/17393 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/10 , H04L49/101 , H04L49/1507 , H04L49/25 , H04L49/506
摘要： Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.
摘要翻译：源电路（10）产生可以由多个处理电路（14）中的任何一个处理的消息。在源电路和处理电路（14）之间提供分配器电路网络。网络中的分配器电路的本地决定决定了消息将被路由到哪个处理电路的每个消息。消息提供给至少两个并行分配器电路。这些分配器电路（12a）基于其他分配器电路（12b）中的各个的当前可用性从网络中的其它分配器电路（12b）中进行选择。根据数据处理电路（14）的当前可用性，各个消息依次由所选择的另外的分配器电路（12b）选择的路径从所选择的另外的分配器电路（12b）转发到数据处理电路（14），以及 /或后续的分配器电路（12c）。

4. 发明申请

US20080311876A1 Signal Receiver for Wideband Wireless Communication 审中-公开
标题翻译：用于宽带无线通信的信号接收机
公开(公告)号：US20080311876A1
公开(公告)日：2008-12-18
申请号：US11910455
申请日：2006-03-16
申请人： Dominicus M.W. Leenaerts , Cornelis H. Van Berkel
发明人： Dominicus M.W. Leenaerts , Cornelis H. Van Berkel
IPC分类号： H04B1/26
CPC分类号： H04B1/0092 , H04B1/28
摘要： A signal receiver for use in a 60 GHz wireless area network, in which the received RF signal band (100) is converted to a plurality of intermediate frequency (IF) sub-bands (104) and then processing (LPF, AGC, ADC) in the analogue domain of the sub-bands (104) is performed in parallel. As a result, the design requirements of the analogue components are significantly relaxed and it is possible to perform gain control in respect of each sub-band (104), which improves the quality of the received signal.
摘要翻译：一种在60GHz无线区域网络中使用的信号接收机，其中接收的RF信号频带（100）被转换成多个中频（IF）子频带（104），然后处理（LPF，AGC，ADC）在子带（104）的模拟域中并行执行。结果，模拟部件的设计要求显着地松弛，并且可以对每个子带（104）执行增益控制，这提高了接收信号的质量。

5. 发明授权

US08135897B2 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US08135897B2
公开(公告)日：2012-03-13
申请号：US12227344
申请日：2007-05-14
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/06
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register. In the fifth step the rotated set of elements are stored in the second memory to obtain a transposed warped diagonal. The second to fifth steps are repeated with the subsequent warp diagonals until matrix transposition is complete.
摘要翻译：介绍了一种内存架构。存储器架构包括第一存储器和第二存储器。第一个存储器至少具有可由单个地址寻址的第一宽度的存储区。第二存储器具有多个第二宽度的组，所述组可由地址向量的组件寻址。第二宽度是第一宽度的至多一半。第一存储器和第二存储器被选择性地耦合，并且所述第一存储器和第二存储器可由地址空间寻址。本发明还提供一种使用存储器架构来转置矩阵的方法，包括以下步骤。在第一步中，矩阵元素从第一存储器移动到第二存储器。在第二步中，沿着矩阵的翘曲对角线布置的一组元件被加载到寄存器中。在第四步骤中，存储在寄存器中的元素集合被旋转，直到来自矩阵的第一行的元素处于寄存器的第一位置。在第五步骤中，将旋转的元件组存储在第二存储器中以获得转置的翘曲对角线。第二至第五步骤随后续的经向对角线重复，直到矩阵转置完成。

6. 发明申请

US20090300310A1 Memory Architecture 有权
标题翻译：内存架构
公开(公告)号：US20090300310A1
公开(公告)日：2009-12-03
申请号：US12227344
申请日：2007-05-14
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/02
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register. In the fifth step the rotated set of elements are stored in the second memory to obtain a transposed warped diagonal. The second to fifth steps are repeated with the subsequent warp diagonals until matrix transposition is complete.
摘要翻译：介绍了一种内存架构。存储器架构包括第一存储器和第二存储器。第一个存储器至少具有可以由单个地址寻址的第一宽度的存储体。第二存储器具有多个第二宽度的组，所述组可由地址向量的组件寻址。第二宽度是第一宽度的至多一半。第一存储器和第二存储器被选择性地耦合，并且所述第一存储器和第二存储器可由地址空间寻址。本发明还提供一种使用存储器架构来转置矩阵的方法，包括以下步骤。在第一步中，矩阵元素从第一存储器移动到第二存储器。在第二步中，沿着矩阵的翘曲对角线布置的一组元件被加载到寄存器中。在第四步骤中，存储在寄存器中的元素集合被旋转，直到来自矩阵的第一行的元素处于寄存器的第一位置。在第五步骤中，将旋转的元件组存储在第二存储器中以获得转置的翘曲对角线。第二至第五步骤随后续的经向对角线重复，直到矩阵转置完成。

7. 发明授权

US5802331A Data processing system comprising an asynchronously controlled pipeline 失效
标题翻译：数据处理系统包括一个异步控制的流水线
公开(公告)号：US5802331A
公开(公告)日：1998-09-01
申请号：US702305
申请日：1996-08-23
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F13/42 , G06F5/06 , G06F9/38 , G06F12/08 , G06F13/14
CPC分类号： G06F9/3869 , G06F9/3871
摘要： A data processing system transports data via successive stages of a pipeline. Whenever possible the stages are in a transparent mode so that data made available can travel through the pipeline with a minimum delay. The arrival of data is signaled by a preceding stage by making the potential on a conductive connection to the stage high. In response thereto the stage switches over to a hold mode which enables new data to be made available on its input even before the data has been passed on. The stage makes the potential on the conductive connection to the next stage high and the potential on the conductive connection to the preceding stage low again, and also sets a register. The register is reset and the stage becomes transparent again as soon as it receives an acknowledge signal from its successor, signifying that the data has been taken up. For as long as the register is in the set state, the stage does not respond to the fact that the potential on the connection to the preceding stage becomes high, except that the stage itself starts to keep the potential on the connection high.
摘要翻译：数据处理系统经由流水线的连续阶段传送数据。只要有可能，这些阶段处于透明模式，以便可用的数据可以以最小的延迟行进通过管道。数据的到达通过在高级的导电连接上产生电位，由前一级发出信号。响应于此，阶段切换到保持模式，即使在数据已经通过之前，也可以在其输入上使新数据可用。该级使导通连接的电位下一级为高电平，并且导通连接到前一级的电位再次为低电平，并且还设置寄存器。寄存器被复位，一旦接收到来自其后继者的确认信号，该阶段再次变得透明，表示数据被占用。只要寄存器处于置位状态，该级不响应与前一级连接的电位变高的事实，只是该级本身开始保持连接高电平。

8. 发明授权

US5280596A Write-acknowledge circuit including a write detector and a bistable element for four-phase handshake signalling 失效
标题翻译：写入确认电路，包括用于四相握手信令的写入检测器和双稳态元件
公开(公告)号：US5280596A
公开(公告)日：1994-01-18
申请号：US659805
申请日：1991-02-21
申请人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs
发明人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs
IPC分类号： G06F13/42 , G11C7/22 , H03K3/037 , H03K3/356 , H03K17/687
CPC分类号： G11C7/22
摘要： A write-acknowledge circuit includes a write detector and a bistable element. The write detector has two write inputs, two complementary inputs and an acknowledge output, and is constituted by only two transistors which are connected in series. The complementary inputs are the control inputs of the two transistors and the acknowledge output is output from their common connection point. The write inputs are respectively coupled to the two remaining terminals of the two transistors and also to the two respective inputs of the bistable element. The complementary inputs are coupled crosswise to the outputs of the bistable element. The write signals represent a 1-bit variable encoded according to the Double-Rail Encoding method. Four-phase handshake signalling is used for the write signals. The acknowledge output is activated by the complementary inputs to the write detector in response to a write signal on either of the two write inputs, the acknowledge signal denoting that the write signal has been processed by the write-acknowledge circuit and so can be permitted to return to a rest value.
摘要翻译：写入确认电路包括写入检测器和双稳态元件。写入检测器具有两个写入输入，两个互补输入和一个应答输出，并且仅由串联连接的两个晶体管构成。互补输入是两个晶体管的控制输入，并且应答输出从其公共连接点输出。写输入分别耦合到两个晶体管的两个剩余端子，并且还耦合到双稳态元件的两个相应的输入端。互补输入与双稳态元件的输出交叉耦合。写信号表示根据双轨编码方法编码的1位变量。四信号握手信号用于写入信号。响应于两个写入输入中的任一个上的写入信号，写入检测器的互补输入激活应答输出，表示写入信号已经被写入确认电路处理的确认信号被允许返回休息值。

9. 发明授权

US4845678A Memory comprising simultaneously addressable memory elements 失效
标题翻译：存储器包括同时可寻址存储器元件
公开(公告)号：US4845678A
公开(公告)日：1989-07-04
申请号：US33126
申请日：1987-03-31
申请人： Cornelis H. van Berkel , Roelof H. W. Salters
发明人： Cornelis H. van Berkel , Roelof H. W. Salters
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06T1/60 , G11C8/10 , G11C11/401 , H03M7/14
CPC分类号： H03M7/14 , G06F12/0207 , G11C8/10
摘要： A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.

10. 发明申请

US20100211749A1 METHOD OF STORING DATA, METHOD OF LOADING DATA AND SIGNAL PROCESSOR 有权
标题翻译：存储数据的方法，数据加载方法和信号处理器
公开(公告)号：US20100211749A1
公开(公告)日：2010-08-19
申请号：US12450819
申请日：2008-04-11
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3885
摘要： A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, —storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).
摘要翻译：描述了一种用于将具有从寄存器文件（RF）到n存储器（M）的n位大小的处理数据元素（D1，...，D8）的向量存储的方法。存储器被布置用于将存储数据元素的矢量存储在具有m位大小的位置（M1，... M5）中，其中m> n。该方法包括以下步骤：在存储在相互后继的寄存器元件中的向量中交换处理数据元素之间的位（S2），产生修改后的数据元素（DmI，...，Dm8），混洗（S3）在所得到的向量中的k个后续比特的组，将修改的数据元素的所得混洗向量（S4）存储（S4）作为存储器（M）中的存储数据元素的向量。

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