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1. 发明授权

US06756184B2 Method of making tall flip chip bumps 失效
标题翻译：制作高倒装芯片凸块的方法
公开(公告)号：US06756184B2
公开(公告)日：2004-06-29
申请号：US09976067
申请日：2001-10-12
申请人： Chiou-Shian Peng , Euegene Chu , Alex Fahn , Kenneth Lin , Gilbert Fane , James Chen , Kuo-Wei Lin
发明人： Chiou-Shian Peng , Euegene Chu , Alex Fahn , Kenneth Lin , Gilbert Fane , James Chen , Kuo-Wei Lin
IPC分类号： G03F700
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/11462 , H01L2224/1147 , H01L2224/11502 , H01L2224/11849 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/11901 , H01L2224/1146
摘要： A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.
摘要翻译：一种在半导体器件上制造改进的高度的导电凸块的方法。该方法包括以下步骤：在半导体器件上沉积凸块下的金属到接触焊盘上; 沉积和图案化光致抗蚀剂层以在凸块下冶金上提供开口; 将第一导电材料沉积到光致抗蚀剂层的开口中; 在所述第一导电材料上沉积第二导电材料; 去除光致抗蚀剂层和过量的凸块下冶金; 将助熔剂施加到所述第二导电材料的顶表面; 硬烘烤半导体器件去除任何氧化物; 将半导体器件的一部分浸入化学镀溶液中; 从化学镀液中除去半导体器件; 并且回流所述导电材料以在所述半导体器件上提供改善高度的突起。

2. 发明授权

US06482669B1 Colors only process to reduce package yield loss 有权
标题翻译：颜色只能减少包装产量损失
公开(公告)号：US06482669B1
公开(公告)日：2002-11-19
申请号：US09867379
申请日：2001-05-30
申请人： Yang-Tung Fan , Chiou-Shian Peng , Cheng-Yu Chu , Shih-Jane Lin , Yen-Ming Chen , Fu-Jier Fan , Kuo-Wei Lin
发明人： Yang-Tung Fan , Chiou-Shian Peng , Cheng-Yu Chu , Shih-Jane Lin , Yen-Ming Chen , Fu-Jier Fan , Kuo-Wei Lin
IPC分类号： H01L2100
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14645 , H01L31/02162 , H01L31/02327
摘要： Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.
摘要翻译：公开了一种有序的微电子制造顺序，其中滤色器通过直角沉积直接形成在CCD，CID或CMOS成像装置的光电检测器阵列上以形成凹入像素表面，并且覆盖有高透光率平面化膜指定的折射率和物理性质，其优化光收集到光电二极管而不需要额外的常规微透镜。光学平坦的顶表面用于封装和保护成像仪免受化学和热清洁处理损伤，最小化形成在非平面表面上的图像的像差或引起反射损失的形貌底层变化，并避免在切割和包装期间引起的残留颗粒夹杂物。通过在半导体衬底上光刻地构图光电二极管平面阵列来形成CCD成像器。光电二极管阵列设置有金属遮光罩，钝化，并且在其上形成滤色器。沉积透明密封剂以平坦化滤色器层并完成固态彩色图像形成装置，而不需要常规的凸起的微透镜。

3. 发明授权

US06372545B1 Method for under bump metal patterning of bumping process 有权
标题翻译：碰撞过程中碰撞下金属图案化的方法
公开(公告)号：US06372545B1
公开(公告)日：2002-04-16
申请号：US09814039
申请日：2001-03-22
申请人： Fu-Jier Fan , Kuo-Wei Lin , Yen-Ming Chen , Cheng-Yu Chu , Shih-Jane Lin , Chiou-Shian Peng , Yang-Tung Fan
发明人： Fu-Jier Fan , Kuo-Wei Lin , Yen-Ming Chen , Cheng-Yu Chu , Shih-Jane Lin , Chiou-Shian Peng , Yang-Tung Fan
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/1147 , H01L2224/11472 , H01L2224/11901 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01072 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/19043 , H01L2924/00014
摘要： A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening. The patterned dry film resistor (DFR) layer is lifted off, along with the metal layer over patterned dry film resistor (DFR) layer and over at least the portion of the opposing side walls, leaving the metal layer over the exposed second portion of the I/O pad. The metal layer over the exposed second portion of the I/O pad being an under bump metal.
摘要翻译：一种形成凸块下金属的方法，包括以下步骤。提供具有暴露的I / O焊盘的半导体结构。图案化的钝化层形成在半导体结构之上，图案化的钝化层具有暴露I / O焊盘的第一部分的开口。将干膜电阻（DFR）层层压，曝光和显影以在图案化的钝化层上形成图案化的干膜电阻（DFR）层。图案化的干膜电阻器（DFR）层具有露出I / O焊盘的第二部分的开口。图案化的干膜电阻（DFR）层开口具有相对的侧壁，具有预定的具有底切的轮廓。在图案化干膜电阻器（DFR）层，I / O焊盘的暴露的第三部分以及图案化干膜电阻器（DFR）层开口的相对侧壁的至少一部分之上形成金属层。图案化的干膜电阻器（DFR）层与图案化的干膜电阻器（DFR）层上的金属层一起被提起并且在至少相对的侧壁的部分之上，使得金属层在暴露的第二部分 I / O焊盘。 I / O焊盘暴露的第二部分上的金属层是凸块下金属。

4. 发明授权

US06211028B1 Twin current bipolar device with hi-lo base profile 有权
标题翻译：双电流双极型器件，具有Hi-lo基座型材
公开(公告)号：US06211028B1
公开(公告)日：2001-04-03
申请号：US09245560
申请日：1999-02-05
申请人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.
摘要翻译：描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

5. 发明授权

US06956292B2 Bumping process to increase bump height and to create a more robust bump structure 有权
标题翻译：凸起过程增加凸块高度并创建更坚固的凸块结构
公开(公告)号：US06956292B2
公开(公告)日：2005-10-18
申请号：US10613694
申请日：2003-07-03
申请人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
发明人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/11 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/1147 , H01L2224/1191 , H01L2224/13099 , H01L2224/45144 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.
摘要翻译：提供了一种新的工艺，其是用于产生焊料凸块的当前处理的延伸和改进。在图形化和蚀刻形式下形成了凹凸金属层和焊料金属层之后，按照传统的处理顺序，沉积了一层聚酰亚胺。使用聚酰亚胺沉积层的厚度来进行焊料流动，以控制在重熔焊料下面的柱的高度。

6. 发明授权

US06586323B1 Method for dual-layer polyimide processing on bumping technology 有权
标题翻译：碰撞技术双层聚酰亚胺加工方法
公开(公告)号：US06586323B1
公开(公告)日：2003-07-01
申请号：US09664417
申请日：2000-09-18
申请人： Fu-Jier Fan , Cheng-Yu Chu , Kuo Wei Lin , Shih-Jang Lin , Yang-Tung Fan , Chiou-Shian Peng
发明人： Fu-Jier Fan , Cheng-Yu Chu , Kuo Wei Lin , Shih-Jang Lin , Yang-Tung Fan , Chiou-Shian Peng
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2224/05552
摘要： A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.
摘要翻译：提供了一种新的方法和处理顺序，用于形成与下面的铝接触焊盘接触的焊料凸块。在图案化的PE Si 3 N 4层和聚酰胺绝缘体的图案化层之间插入负型光致抗蚀剂的图案层。图案化的负光致抗蚀剂部分覆盖铝接触垫，并防止聚酰胺绝缘体层与铝接触垫之间的接触。通过形成该屏障，聚酰胺绝缘体中所含的水分不能与铝接触垫接触，因此铝接触垫的表面中不会发生腐蚀。

7. 发明授权

US06958546B2 Method for dual-layer polyimide processing on bumping technology 失效
标题翻译：碰撞技术双层聚酰亚胺加工方法
公开(公告)号：US06958546B2
公开(公告)日：2005-10-25
申请号：US10437373
申请日：2003-05-13
申请人： Fu-Jier Fan , Cheng-Yu Chu , Kuo Wei Lin , Shih-Jang Lin , Yang-Tung Fran , Chiou-Shian Peng
发明人： Fu-Jier Fan , Cheng-Yu Chu , Kuo Wei Lin , Shih-Jang Lin , Yang-Tung Fran , Chiou-Shian Peng
IPC分类号： H01L21/60 , H01L23/485 , H01L23/48
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2224/05552
摘要： A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.
摘要翻译：提供了一种新的方法和处理顺序，用于形成与下面的铝接触焊盘接触的焊料凸块。负型光致抗蚀剂的图案化层插入在PE 3 N 4 N 4的图案化层和聚酰胺绝缘体的图案化层之间。图案化的负光致抗蚀剂部分覆盖铝接触垫，并防止聚酰胺绝缘体层与铝接触垫之间的接触。通过形成该屏障，聚酰胺绝缘体中所含的水分不能与铝接触垫接触，因此铝接触垫的表面中不会发生腐蚀。

8. 发明授权

US06876049B2 Colors only process to reduce package yield loss 失效
公开(公告)号：US06876049B2
公开(公告)日：2005-04-05
申请号：US10272136
申请日：2002-10-16
申请人： Yang-Tung Fan , Chiou-Shian Peng , Cheng-Yu Chu , Shih-Jane Lin , Yen-Ming Chen , Fu-Jier Fan , Kuo-Wei Lin
发明人： Yang-Tung Fan , Chiou-Shian Peng , Cheng-Yu Chu , Shih-Jane Lin , Yen-Ming Chen , Fu-Jier Fan , Kuo-Wei Lin
IPC分类号： G02F1/1335 , H01L21/00 , H01L27/146 , H01L31/0216 , H01L31/0232
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14645 , H01L31/02162 , H01L31/02327
摘要： Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

9. 发明授权

US06649507B1 Dual layer photoresist method for fabricating a mushroom bumping plating structure 有权
标题翻译：双层光刻胶法制造蘑菇凸版电镀结构
公开(公告)号：US06649507B1
公开(公告)日：2003-11-18
申请号：US09883163
申请日：2001-06-18
申请人： Yen-Ming Chen , Cheng-Yu Chu , Kuo-Wei Lin , Chiou-Shian Peng , Yang-Tung Fan , Fu-Jier Fan , Shih-Jane Lin
发明人： Yen-Ming Chen , Cheng-Yu Chu , Kuo-Wei Lin , Chiou-Shian Peng , Yang-Tung Fan , Fu-Jier Fan , Shih-Jane Lin
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13006 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/01083
摘要： A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.
摘要翻译：一种形成凸块结构的方法，包括以下步骤。提供具有暴露的第一导电结构的结构。在结构和暴露的第一导电结构上形成第一光致抗蚀剂层。在第一光致抗蚀剂层上形成第二覆盖光致抗蚀剂层。第一和第二光致抗蚀剂层由不同的光致抗蚀剂材料组成。图案化第一和第二光致抗蚀剂层以形成穿过第一和第二光致抗蚀剂层并在第一导电结构上的开口。第二覆盖光致抗蚀剂层防止在处理期间过度形成第一光致抗蚀剂层残留物。在开口内形成第二导电结构。剥离第一和第二图案化的光致抗蚀剂层。第二导电结构被回流以形成凸块结构。

10. 发明授权

US06605524B1 Bumping process to increase bump height and to create a more robust bump structure 有权
标题翻译：凸起过程增加凸块高度并创建更坚固的凸块结构
公开(公告)号：US06605524B1
公开(公告)日：2003-08-12
申请号：US09950227
申请日：2001-09-10
申请人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
发明人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/1147 , H01L2224/1191 , H01L2224/13099 , H01L2224/45144 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.
摘要翻译：提供了一种新的工艺，其是用于产生焊料凸块的当前处理的延伸和改进。在图形化和蚀刻形式下形成了凹凸金属层和焊料金属层之后，按照传统的处理顺序，沉积了一层聚酰亚胺。使用聚酰亚胺沉积层的厚度来进行焊料流动，以控制在重熔焊料下面的柱的高度。

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