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    • 5. 发明申请
    • Fast DCT method and apparatus for digital video compression
    • 用于数字视频压缩的快速DCT方法和装置
    • US20050074062A1
    • 2005-04-07
    • US10678916
    • 2003-10-06
    • Chih-Ta SungChun Lien
    • Chih-Ta SungChun Lien
    • H04N7/12H04N7/30
    • H04N19/124H04N19/176H04N19/60
    • The present invention provides method and apparatus of a fast DCT implementation. DCT calculation is combined with quantization scales by a procedure of pre-processing. During DCT coefficient calculation, only non-zero coefficients are calculated. If pixel variance range is smaller than a first predetermined threshold, a predetermined lookup table is compared to decide the DCT coefficients. When a pixel variance range of a block pixels is within the second threshold, coupled with the quantization scales, the pre-processing determines the amount of non-zero DCT coefficients need to be calculated. Only a limited amount of LSB bits within a block is applied in the calculation of DCT coefficients. A previously saved pixel with equal or closest pixel value is used to replace the operation of current pixel's multiplication.
    • 本发明提供了快速DCT实现的方法和装置。 通过预处理过程将DCT计算与量化尺度相结合。 在DCT系数计算期间,仅计算非零系数。 如果像素方差范围小于第一预定阈值,则比较预定查找表以确定DCT系数。 当块像素的像素方差范围在第二阈值内时,与量化尺度相结合,预处理确定需要计算的非零DCT系数的量。 在DCT系数的计算中仅应用块内的有限数量的LSB位。 使用具有相等或最接近像素值的先前保存的像素来代替当前像素的乘法运算。
    • 9. 发明授权
    • Reset based computer bus identification method and circuit resilient to
power transience
    • 基于复位的计算机总线识别方法和电路适应电力瞬态
    • US5608877A
    • 1997-03-04
    • US409243
    • 1995-03-24
    • Chih-Ta SungTzoyao ChanJih-Hsien Soong
    • Chih-Ta SungTzoyao ChanJih-Hsien Soong
    • G06F13/40G06F13/00G06F13/42
    • G06F13/4068
    • An automatic bus identification circuit is provided in a device to reliably detect system bus type on power up despite fluctuations in supply voltage. A system bus type signal is received over a multi-function input line at a first input and a reset signal received over a set line at a second input. A bus type identification circuitry is provided to latch the system bus type signal upon power up and continuously output this signal as a system bus type identification signal. To prevent the influence of disturbances in the power supply upon power-up, a flip-flip is provided to output a logic signal in response to a system reset signal. The flip-flop is configured with a strong-N type inverter to insure that the flip-flop will be set into a grounded state as power is applied to the circuit, despite the influence of transient power supply voltages.
    • 在设备中提供自动总线识别电路,以尽可能地供电电压波动来可靠地检测上电时的系统总线类型。 系统总线类型信号通过第一输入端的多功能输入线路接收,并在第二输入端通过设定线路接收复位信号。 提供总线类型识别电路,用于在上电时锁存系统总线类型信号,并将该信号连续输出为系统总线类型识别信号。 为了防止上电时电源干扰的影响,提供触发翻转以响应于系统复位信号输出逻辑信号。 触发器配置有强N型反相器,以确保触发器将被设置为接地状态,尽管施加到电路的功率,尽管瞬态电源电压的影响。