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1. 发明授权

US08507988B2 High voltage devices, systems, and methods for forming the high voltage devices 有权
标题翻译：用于形成高压器件的高压器件，系统和方法
公开(公告)号：US08507988B2
公开(公告)日：2013-08-13
申请号：US12792055
申请日：2010-06-02
申请人： Chih-Wen Yao , Robert S. J. Pan , Ruey-Hsin Liu , Hsueh-Liang Chou , Puo-Yu Chiang , Chi-Chih Chen , Hsiao Chin Tuan
发明人： Chih-Wen Yao , Robert S. J. Pan , Ruey-Hsin Liu , Hsueh-Liang Chou , Puo-Yu Chiang , Chi-Chih Chen , Hsiao Chin Tuan
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689
摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.
摘要翻译：高压（HV）器件包括在衬底上的栅极电介质结构。栅介质结构具有第一部分和第二部分。第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。第一厚度大于第二厚度。栅电极设置在栅介电结构上。一个金属层结合在栅电极上。金属层沿栅极电介质结构下方的沟道的方向延伸。至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

2. 发明申请

US20130181285A1 Lateral DMOS Device with Dummy Gate 有权
标题翻译：具有虚拟门的侧面DMOS设备
公开(公告)号：US20130181285A1
公开(公告)日：2013-07-18
申请号：US13351295
申请日：2012-01-17
申请人： Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
发明人： Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/42368
摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.
摘要翻译：具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层在扩展漂移区域上。具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

3. 发明申请

US20110079846A1 HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES 有权
标题翻译：用于形成高电压装置的高压装置，系统和方法
公开(公告)号：US20110079846A1
公开(公告)日：2011-04-07
申请号：US12792055
申请日：2010-06-02
申请人： Chih-Wen YAO , Robert S. J. Pan , Ruey-Hsin LIU , Hsueh-Liang CHOU , Puo-Yu CHIANG , Chi-Chih CHEN , Hsiao Chin TUAN
发明人： Chih-Wen YAO , Robert S. J. Pan , Ruey-Hsin LIU , Hsueh-Liang CHOU , Puo-Yu CHIANG , Chi-Chih CHEN , Hsiao Chin TUAN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689
摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.
摘要翻译：高压（HV）器件包括在衬底上的栅极电介质结构。栅介质结构具有第一部分和第二部分。第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。第一厚度大于第二厚度。栅电极设置在栅介电结构上。一个金属层结合在栅电极上。金属层沿栅极电介质结构下方的沟道的方向延伸。至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

4. 发明申请

US20070170469A1 LDMOS device with improved ESD performance 有权
标题翻译： LDMOS器件具有改进的ESD性能
公开(公告)号：US20070170469A1
公开(公告)日：2007-07-26
申请号：US11337147
申请日：2006-01-20
申请人： Kuo-Ming Wu , Jian-Hsing Lee , Yi-Chun Lin , Chi-Chih Chen
发明人： Kuo-Ming Wu , Jian-Hsing Lee , Yi-Chun Lin , Chi-Chih Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/0882 , H01L29/4238
摘要： A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.
摘要翻译：半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

5. 发明申请

US20080237703A1 HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：高电压半导体器件及其制造方法
公开(公告)号：US20080237703A1
公开(公告)日：2008-10-02
申请号：US11692213
申请日：2007-03-28
申请人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/0886 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.
摘要翻译：能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。在掺杂体区和阱区之间不存在P-N结。

6. 发明申请

US20060022866A1 Vehicle obstacle warning radar 有权
标题翻译：车辆障碍物警示雷达
公开(公告)号：US20060022866A1
公开(公告)日：2006-02-02
申请号：US10968472
申请日：2004-10-19
申请人： Eric Walton , Chi-Chih Chen
发明人： Eric Walton , Chi-Chih Chen
IPC分类号： G01S13/93 , G01S7/28
CPC分类号： G01S7/352 , G01S3/48 , G01S5/04 , G01S13/003 , G01S13/32 , G01S13/46 , G01S13/931 , G01S2007/358 , G01S2007/4086 , G01S2013/0245 , G01S2013/0254 , G01S2013/9332 , G01S2013/9375 , G01S2013/9385 , G01S2013/9389 , H01Q1/3233 , H01Q1/3283 , H01Q9/0407 , H01Q21/08 , H01Q23/00
摘要： The present invention is a radar system for detecting the presence of obstacles. The radar system includes at least one transmitting antenna and at least one receiving antenna. The transmitting antenna receives an input signal and transmits an electromagnetic wave. The electromagnetic wave reflects off an obstacle back to the receiving antenna. The receiving antenna captures the reflected electromagnetic wave and produces an output signal. The output signal is then combined with the local reference signal in a quadrature mixer. The resulting in-phase (I) and quadrature (Q) signals may be further processed and then transmitted to a processing system. The processing system uses a suitable algorithm, e.g., a back projection algorithm, to estimate the type and location of obstacles that reflected the electromagnetic wave. In an exemplary embodiment, the algorithm is adapted to discriminate between different sizes and locations of obstacles in order to determine if there is a hazard. Based on this information, the processing system then communicates with a visual and/or audible warning system in order to alert the driver about the obstacle if it has been determined to be a hazard.
摘要翻译：本发明是用于检测障碍物的存在的雷达系统。雷达系统包括至少一个发射天线和至少一个接收天线。发送天线接收输入信号并发送电磁波。电磁波从障碍物反射回接收天线。接收天线捕获反射的电磁波并产生输出信号。然后将输出信号与正交混频器中的本地参考信号组合。可以进一步处理所得到的同相（I）和正交（Q）信号，然后将其发送到处理系统。处理系统使用合适的算法，例如反投影算法来估计反映电磁波的障碍物的类型和位置。在示例性实施例中，该算法适于区分障碍物的不同大小和位置，以便确定是否存在危险。基于该信息，处理系统然后与视觉和/或听觉警报系统进行通信，以便如果已被确定为危险，则警告驾驶员关于障碍物。

7. 发明授权

US09818859B2 Quasi-vertical power MOSFET and methods of forming the same 有权
公开(公告)号：US09818859B2
公开(公告)日：2017-11-14
申请号：US13219283
申请日：2011-08-26
申请人： Chi-Chih Chen , Kun-Hsuan Tien , Ruey-Hsin Liu
发明人： Chi-Chih Chen , Kun-Hsuan Tien , Ruey-Hsin Liu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/423 , H01L29/08
CPC分类号： H01L29/7809 , H01L29/0878 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.

8. 发明授权

US09450056B2 Lateral DMOS device with dummy gate 有权
标题翻译：具有虚拟门的侧面DMOS设备
公开(公告)号：US09450056B2
公开(公告)日：2016-09-20
申请号：US13351295
申请日：2012-01-17
申请人： Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
发明人： Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
IPC分类号： H01L29/78 , H01L29/40 , H01L29/423 , H01L29/06
CPC分类号： H01L29/7816 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/42368
摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.
摘要翻译：具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层在扩展漂移区域上。具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

9. 发明申请

US20120273883A1 HIGH VOLTAGE DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：高电压装置及其形成方法
公开(公告)号：US20120273883A1
公开(公告)日：2012-11-01
申请号：US13096117
申请日：2011-04-28
申请人： Shiang-Yu CHEN , Chi-Chih CHEN , Kuo-Ming WU
发明人： Shiang-Yu CHEN , Chi-Chih CHEN , Kuo-Ming WU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42368 , H01L29/0653 , H01L29/0692 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is disposed over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is disposed over a second well region of a second dopant type. The first thickness is larger than the second thickness. An isolation structure is disposed between the gate dielectric structure and a drain region disposed within the first well region. A gate electrode is disposed over the gate dielectric structure.
摘要翻译：高压（HV）器件包括在衬底上的栅极电介质结构。栅介质结构具有第一部分和第二部分。第一部分具有第一厚度并且设置在衬底中的第一掺杂剂类型的第一阱区域之上。第二部分具有第二厚度并且设置在第二掺杂剂类型的第二阱区上。第一厚度大于第二厚度。隔离结构设置在栅极电介质结构和设置在第一阱区内的漏极区之间。栅电极设置在栅介电结构上。

10. 发明授权

US07420252B2 LDMOS device with improved ESD performance 有权
标题翻译： LDMOS器件具有改进的ESD性能
公开(公告)号：US07420252B2
公开(公告)日：2008-09-02
申请号：US11337147
申请日：2006-01-20
申请人： Kuo-Ming Wu , Jian-Hsing Lee , Yi-Chun Lin , Chi-Chih Chen
发明人： Kuo-Ming Wu , Jian-Hsing Lee , Yi-Chun Lin , Chi-Chih Chen
IPC分类号： H01L23/62
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/0882 , H01L29/4238
摘要： A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.
摘要翻译：半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

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