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1. 发明授权

US08633086B2 Power devices having reduced on-resistance and methods of their manufacture 有权
标题翻译：功率器件具有降低的导通电阻及其制造方法
公开(公告)号：US08633086B2
公开(公告)日：2014-01-21
申请号：US12651322
申请日：2009-12-31
申请人： Alex Kalnitsky , Hsiao-Chin Tuan , Liang-Kai Han , Uway Tseng , Yuan-Chih Hsieh , Hung-Hua Lin
发明人： Alex Kalnitsky , Hsiao-Chin Tuan , Liang-Kai Han , Uway Tseng , Yuan-Chih Hsieh , Hung-Hua Lin
IPC分类号： H01L21/30
CPC分类号： H01L29/66712 , H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.
摘要翻译：提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。将晶片减薄至预定厚度。多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

2. 发明授权

US08507988B2 High voltage devices, systems, and methods for forming the high voltage devices 有权
标题翻译：用于形成高压器件的高压器件，系统和方法
公开(公告)号：US08507988B2
公开(公告)日：2013-08-13
申请号：US12792055
申请日：2010-06-02
申请人： Chih-Wen Yao , Robert S. J. Pan , Ruey-Hsin Liu , Hsueh-Liang Chou , Puo-Yu Chiang , Chi-Chih Chen , Hsiao Chin Tuan
发明人： Chih-Wen Yao , Robert S. J. Pan , Ruey-Hsin Liu , Hsueh-Liang Chou , Puo-Yu Chiang , Chi-Chih Chen , Hsiao Chin Tuan
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689
摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.
摘要翻译：高压（HV）器件包括在衬底上的栅极电介质结构。栅介质结构具有第一部分和第二部分。第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。第一厚度大于第二厚度。栅电极设置在栅介电结构上。一个金属层结合在栅电极上。金属层沿栅极电介质结构下方的沟道的方向延伸。至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

3. 发明申请

US20130140667A1 LOCALIZED CARRIER LIFETIME REDUCTION 有权
标题翻译：本地化运输车减少生命周期
公开(公告)号：US20130140667A1
公开(公告)日：2013-06-06
申请号：US13308957
申请日：2011-12-01
申请人： Alex KALNITSKY , Chih-Wen YAO , Jun CAI , Ruey-Hsin LIU , Hsiao-Chin TUAN
发明人： Alex KALNITSKY , Chih-Wen YAO , Jun CAI , Ruey-Hsin LIU , Hsiao-Chin TUAN
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L21/76237 , H01L21/26506 , H01L21/26586 , H01L21/76216 , H01L21/823456 , H01L21/823481 , H01L21/82385 , H01L21/823878 , H01L27/0921 , H01L29/1087
摘要： A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.
摘要翻译：半导体结构包括衬底，第一功率器件和衬底中的第二功率器件，第一和第二功率器件之间的至少一个隔离特征以及邻接衬底中的至少一个隔离特征的俘获特征。

4. 发明申请

US20130134512A1 Power MOSFETs and Methods for Forming the Same 有权
标题翻译：功率MOSFET及其形成方法
公开(公告)号：US20130134512A1
公开(公告)日：2013-05-30
申请号：US13348463
申请日：2012-01-11
申请人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu , Hsiao-Chin Tuan
发明人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu , Hsiao-Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0634 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/456 , H01L29/66659
摘要： A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate
摘要翻译：功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。栅极电介质和栅电极设置在半导体区域上。与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。电介质层具有在漂移区的顶表面上方并与其接触的部分。导电场板在电介质层的上方。源极区域和漏极区域在栅电极的相对侧上。漏极区域与第一漂移区域接触。底部金属层在场板上

5. 发明申请

US20110260245A1 Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device 审中-公开
标题翻译：功率集成电路器件的成本效益全局隔离和功耗
公开(公告)号：US20110260245A1
公开(公告)日：2011-10-27
申请号：US12766454
申请日：2010-04-23
申请人： Ruey-Hsin LIU , Puo-Yu CHIANG , Chih-Wen YAO , Yu-Chang JONG , Hsiao-Chin TUAN
发明人： Ruey-Hsin LIU , Puo-Yu CHIANG , Chih-Wen YAO , Yu-Chang JONG , Hsiao-Chin TUAN
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L27/088 , H01L21/76289 , H01L21/823481 , H01L29/0623 , H01L29/0653 , H01L29/7816
摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. In an embodiment, an apparatus includes a substrate having a first surface and a second surface, the second surface being opposite the first surface; a first device and a second device overlying the substrate; and an isolation structure that extends through the substrate from the first surface to the second surface and between the first device and the second device.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。在一个实施例中，一种装置包括具有第一表面和第二表面的基底，第二表面与第一表面相对; 覆盖衬底的第一器件和第二器件; 以及隔离结构，其从所述第一表面延伸穿过所述基板到所述第二表面以及所述第一装置和所述第二装置之间。

6. 发明申请

US20110220995A1 Semiconductor Device Having Multi-Thickness Gate Dielectric 有权
标题翻译：具有多层栅极电介质的半导体器件
公开(公告)号：US20110220995A1
公开(公告)日：2011-09-15
申请号：US12721045
申请日：2010-03-10
申请人： Hsueh-Liang Chou , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao-Chin Tuan
发明人： Hsueh-Liang Chou , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao-Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42368 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。该器件包括形成在半导体衬底上的半导体衬底和栅极结构。栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。第二厚度大于第一厚度。栅电极设置在第一和第二部分上。在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。还提供了一种制造该方法的方法。

7. 发明申请

US20110079846A1 HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES 有权
标题翻译：用于形成高电压装置的高压装置，系统和方法
公开(公告)号：US20110079846A1
公开(公告)日：2011-04-07
申请号：US12792055
申请日：2010-06-02
申请人： Chih-Wen YAO , Robert S. J. Pan , Ruey-Hsin LIU , Hsueh-Liang CHOU , Puo-Yu CHIANG , Chi-Chih CHEN , Hsiao Chin TUAN
发明人： Chih-Wen YAO , Robert S. J. Pan , Ruey-Hsin LIU , Hsueh-Liang CHOU , Puo-Yu CHIANG , Chi-Chih CHEN , Hsiao Chin TUAN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689
摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.
摘要翻译：高压（HV）器件包括在衬底上的栅极电介质结构。栅介质结构具有第一部分和第二部分。第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。第一厚度大于第二厚度。栅电极设置在栅介电结构上。一个金属层结合在栅电极上。金属层沿栅极电介质结构下方的沟道的方向延伸。至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

8. 发明申请

US20100219463A1 QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE 有权
标题翻译：高电压MOS器件的垂直结构
公开(公告)号：US20100219463A1
公开(公告)日：2010-09-02
申请号：US12699397
申请日：2010-02-03
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.
摘要翻译：半导体器件提供高击穿电压和低导通电阻。该装置包括：基板; 埋设在衬底中的n +层; 设置在掩埋的n +层上的n外延层; 设置在n外延层中的p阱; 源极n +区域，设置在p阱中并连接到一侧的源极触点; 设置在p阱和n外延层顶部的第一绝缘层; 设置在所述第一绝缘层的顶部上的栅极; 以及从掩埋n +层延伸到漏极接触的金属电极，其中金属电极通过第二绝缘层与n外延层和p阱绝缘。

9. 发明授权

US5840605A Dual layer polysilicon capacitor node DRAM process 失效
标题翻译：双层多晶硅电容器节点DRAM工艺
公开(公告)号：US5840605A
公开(公告)日：1998-11-24
申请号：US47397
申请日：1993-04-19
申请人： Hsiao-Chin Tuan
发明人： Hsiao-Chin Tuan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A gate silicon oxide layer is formed on the silicon substrate. A doped layer of polysilicon is formed over the gate silicon oxide layer. The polysilicon layer is patterned to provide the gate electrodes of the transistor. Source/drain regions are formed through ion implantation followed by spacer formation. A node contact oxide is blanket deposited and an opening is formed therein to the silicon substrate at the location of the buried contact. A dual layer of polysilicon is deposited over the node contact oxide and within the opening to the substrate. This dual layer consists of a bottom layer of undoped polysilicon and a top layer of in-situ doped polysilicon wherein the relative thicknesses of the two layers have been determined to optimize both concentration of dopant at the surface of the capacitor node and junction depth. The substrate is annealed to drive in the buried junction. The dual polysilicon layers are patterned to form the capacitor node. A capacitor dielectric is deposited followed by an in-situ doped polysilicon layer which will form the top capacitor plate. An insulating layer is blanket deposited. An opening is made in the insulating layer to the capacitor plate at the boundary of the cell layer. The contact is completed by the deposition and patterning of a metal layer to complete construction of the capacitor, gate electrode, and source/drain structures with buried contacts.
摘要翻译：在硅衬底上形成栅氧化硅层。在栅极氧化硅层上形成掺杂多晶硅层。图案化多晶硅层以提供晶体管的栅电极。源极/漏极区域通过离子注入形成，然后形成间隔物。节点接触氧化物是被覆盖的，并且在掩埋触点的位置处向硅衬底形成开口。双层多晶硅沉积在节点接触氧化物上并且在开口内沉积到衬底上。该双层由未掺杂多晶硅的底层和原位掺杂多晶硅的顶层组成，其中已确定两层的相对厚度以优化电容器节点表面处的掺杂剂的浓度和结深度。将衬底退火以在掩埋结中驱动。图案化双重多晶硅层以形成电容器节点。沉积电容器电介质，然后沉积形成顶部电容器板的原位掺杂多晶硅层。绝缘层被毯子沉积。在电池层的边界处，在电容器板的绝缘层上形成开口。通过金属层的沉积和图案化来完成接触，以完成具有埋入触点的电容器，栅极电极和源极/漏极结构的构造。

10. 发明授权

US5429714A Fabrication method to produce pit-free polysilicon buffer local oxidation isolation 失效
标题翻译：制造无孔多晶硅缓冲区局部氧化隔离的方法
公开(公告)号：US5429714A
公开(公告)日：1995-07-04
申请号：US251191
申请日：1994-05-31
申请人： Hsiao-Chin Tuan , Hu H. Chao
发明人： Hsiao-Chin Tuan , Hu H. Chao
IPC分类号： H01L21/32 , H01L21/00
CPC分类号： H01L21/32
摘要： A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.
摘要翻译：在硅晶片的表面上形成氧化硅隔离区的方法，所述硅晶片由晶圆上的薄氧化硅组成，杂质掺杂多晶硅层和氮化硅层组成。通过图案化氮化硅层和掺杂多晶硅层的至少一部分来形成氧化掩模。氧化硅场隔离区域通过使结构体经受热氧化环境而形成。在一个连续蚀刻步骤中使用单一蚀刻剂除去氧化掩模，所述蚀刻剂例如以基本上相同的速率蚀刻氮化硅和多晶硅层的磷酸，以完成隔离区的形成，而不会点蚀单晶衬底。

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