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1. 发明授权

US09653459B2 MOSFET having source region formed in a double wells region 有权
公开(公告)号：US09653459B2
公开(公告)日：2017-05-16
申请号：US13541539
申请日：2012-07-03
申请人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
发明人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L29/08 , H01L27/092 , H01L29/06 , H01L21/761
CPC分类号： H01L29/1083 , H01L21/761 , H01L27/088 , H01L27/092 , H01L29/0623 , H01L29/0638 , H01L29/0653 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/66659 , H01L29/7816 , H01L29/7833 , H01L29/7835
摘要： A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

2. 发明授权

US09391159B2 Triple well isolated diode and method of making 有权
标题翻译：三重隔离二极管及其制作方法
公开(公告)号：US09391159B2
公开(公告)日：2016-07-12
申请号：US13438600
申请日：2012-04-03
申请人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu
发明人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu
IPC分类号： H01L29/66 , H01L29/06 , H01L29/861 , H02M3/156
CPC分类号： H01L29/6625 , H01L21/76895 , H01L23/535 , H01L29/0607 , H01L29/0653 , H01L29/66136 , H01L29/735 , H01L29/861 , H02M3/156
摘要： A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.
摘要翻译：一种三阱隔离二极管，其包括具有第一导电类型的衬底和形成在衬底中的掩埋层，其中掩埋层具有第二导电类型。三阱隔离二极管包括在衬底上形成的外延层和掩埋层，其中外延层具有第一导电类型。三阱隔离二极管包括在外延层中形成的第一阱，其中第一阱具有第二导电类型，第二阱形成在外延层中，其中第二阱具有第一导电类型并且围绕第一阱，形成在外延层中的第三阱，其中第三阱具有第二导电类型并且围绕第二阱。三阱隔离二极管包括在外延层中形成的深阱，其中深阱具有第一导电类型并且在第一阱下方延伸。

3. 发明授权

US09293376B2 Apparatus and method for power MOS transistor 有权
标题翻译：功率MOS晶体管的装置和方法
公开(公告)号：US09293376B2
公开(公告)日：2016-03-22
申请号：US13546824
申请日：2012-07-11
申请人： Po-Chih Su , Hsueh-Liang Chou , Chun-Wai Ng , Ruey-Hsin Liu
发明人： Po-Chih Su , Hsueh-Liang Chou , Chun-Wai Ng , Ruey-Hsin Liu
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/40 , H01L29/423 , H01L29/78 , H01L21/265 , H01L21/28 , H01L29/08
CPC分类号： H01L29/66734 , H01L21/26586 , H01L21/266 , H01L21/2815 , H01L21/823456 , H01L21/823462 , H01L21/823487 , H01L21/823493 , H01L29/0886 , H01L29/1095 , H01L29/401 , H01L29/407 , H01L29/4236 , H01L29/42376 , H01L29/781 , H01L29/7813 , H01L29/7816 , H01L29/7835
摘要： A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region.
摘要翻译：功率MOS晶体管包括形成在衬底的第一侧上的漏极接触插塞，形成在衬底的第二侧上的源极接触插塞和形成在第一漏极/源极区域和第二漏极/源极区域之间的沟槽。沟槽包括第一栅电极和第二栅电极，其中第一栅电极和第二栅电极的顶表面与漏区的底表面对准。沟槽还包括形成在第一栅极电极和第二栅极电极之间的场板，其中场板电耦合到源极区域。

4. 发明授权

US08704312B2 High voltage devices and methods of forming the high voltage devices 有权
标题翻译：高电压装置及形成高压装置的方法
公开(公告)号：US08704312B2
公开(公告)日：2014-04-22
申请号：US12652294
申请日：2010-01-05
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L24/16 , H01L24/48 , H01L29/063 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01068 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.
摘要翻译：高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。隔离结构至少部分地设置在第一掺杂剂类型的阱区中。第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。

5. 发明授权

US08664741B2 High voltage resistor with pin diode isolation 有权
标题翻译：具有二极管二极管隔离的高压电阻
公开(公告)号：US08664741B2
公开(公告)日：2014-03-04
申请号：US13160030
申请日：2011-06-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/02
CPC分类号： H01L29/0649 , H01L21/26513 , H01L21/74 , H01L21/761 , H01L21/76202 , H01L23/528 , H01L27/0676 , H01L27/0802 , H01L28/20 , H01L29/0692 , H01L29/456 , H01L29/6609 , H01L29/8605 , H01L29/868
摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
摘要翻译：提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。半导体器件包括形成在绝缘结构上的细长电阻器件。电阻器件分别设置在电阻器件的相对端处的第一和第二部分。半导体器件包括形成在电阻器件上的互连结构。互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

6. 发明授权

US08664718B2 Power MOSFETs and methods for forming the same 有权
标题翻译：功率MOSFET及其形成方法
公开(公告)号：US08664718B2
公开(公告)日：2014-03-04
申请号：US13348463
申请日：2012-01-11
申请人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu , Hsiao-Chin Tuan
发明人： Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu , Hsiao-Chin Tuan
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0634 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/456 , H01L29/66659
摘要： A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.
摘要翻译：功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。栅极电介质和栅电极设置在半导体区域上。与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。电介质层具有在漂移区的顶表面上方并与其接触的部分。导电场板在电介质层的上方。源极区域和漏极区域在栅电极的相对侧上。漏极区域与第一漂移区域接触。底部金属层在场板上。

7. 发明申请

US20140015047A1 Integrated Circuit Having a Vertical Power MOS Transistor 有权
标题翻译：具有垂直功率MOS晶体管的集成电路
公开(公告)号：US20140015047A1
公开(公告)日：2014-01-16
申请号：US13588070
申请日：2012-08-17
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/30604 , H01L21/76224 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L21/82385 , H01L21/823878 , H01L21/823885 , H01L21/823892 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/4236 , H01L29/42364 , H01L29/66621 , H01L29/66666 , H01L29/78 , H01L29/7813 , H01L29/7827
摘要： An integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of a same depth as the first trench.
摘要翻译：集成电路包括形成在同一半导体管芯中的多个横向器件和准垂直器件。准垂直装置包括两个沟槽。在第一漏极/源极区域和第二漏极/源极区域之间形成第一沟槽。第一沟槽包括形成在第一沟槽的底部中的介质层和形成在第一沟槽的上部中的栅极区域。第二沟槽形成在与第一沟槽的第二漏极/源极区域相对的一侧上。第二沟槽耦合在第二漏极/源极区域和掩埋层之间，其中第二沟槽具有与第一沟槽相同的深度。

8. 发明申请

US20130320435A1 Trench Power MOSFET 有权
公开(公告)号：US20130320435A1
公开(公告)日：2013-12-05
申请号：US13486681
申请日：2012-06-01
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/02233 , H01L21/26586 , H01L21/266 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/66727 , H01L29/7813
摘要： A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

9. 发明授权

US08461647B2 Semiconductor device having multi-thickness gate dielectric 有权
标题翻译：具有多层栅极电介质的半导体器件
公开(公告)号：US08461647B2
公开(公告)日：2013-06-11
申请号：US12721045
申请日：2010-03-10
申请人： Hsueh-Liang Chou , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao-Chin Tuan
发明人： Hsueh-Liang Chou , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao-Chin Tuan
IPC分类号： H01L29/66
CPC分类号： H01L29/42368 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。该器件包括形成在半导体衬底上的半导体衬底和栅极结构。栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。第二厚度大于第一厚度。栅电极设置在第一和第二部分上。在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。还提供了一种制造该方法的方法。

10. 发明授权

US08445955B2 Quasi-vertical structure for high voltage MOS device 有权
标题翻译：高电压MOS器件的准垂直结构
公开(公告)号：US08445955B2
公开(公告)日：2013-05-21
申请号：US12699397
申请日：2010-02-03
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.
摘要翻译：半导体器件提供高击穿电压和低导通电阻。该装置包括：基板; 埋设在衬底中的n +层; 设置在掩埋的n +层上的n外延层; 设置在n外延层中的p阱; 源极n +区域，设置在p阱中并连接到一侧的源极触点; 设置在p阱和n外延层顶部的第一绝缘层; 设置在所述第一绝缘层的顶部上的栅极; 以及从掩埋n +层延伸到漏极接触的金属电极，其中金属电极通过第二绝缘层与n外延层和p阱绝缘。

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