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1. 发明申请

US20130249615A1 DIGITAL SENSING APPARATUS AND DIGITAL READOUT MODULE THEREOF 有权
标题翻译：数字感应器和数字读出模块
公开(公告)号：US20130249615A1
公开(公告)日：2013-09-26
申请号：US13616606
申请日：2012-09-14
申请人： Kelvin Yi-Tse LAI , Chen-Yi LEE
发明人： Kelvin Yi-Tse LAI , Chen-Yi LEE
IPC分类号： H03K3/017
CPC分类号： G01R23/15 , G01D5/243 , G01P15/125 , G01P21/00 , G01R23/10 , G01R25/08 , G01R29/023 , G01R29/027
摘要： A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.
摘要翻译：数字感测装置包括能够提供与环境参数相关联的感测响应的感测单元和包括用于产生具有与感测响应相关的脉冲宽度的脉冲信号的读取单元的数字读出模块和转换单元。转换单元包括用于产生可变频率时钟信号的时钟信号发生器和可用于使用时钟信号对脉冲信号的脉冲宽度的宽度值进行计数的计数器，以便产生数字感测代码。来自时钟信号发生器的时钟信号的频率可调，以调节脉冲信号脉冲宽度宽度值的分辨率。

2. 发明申请

US20130038369A1 Delay Cell and Digitally Controlled Oscillator 有权
标题翻译：延迟单元和数字控制振荡器
公开(公告)号：US20130038369A1
公开(公告)日：2013-02-14
申请号：US13352350
申请日：2012-01-18
申请人： Chen-Yi LEE , Chien-Ying YU , Chia-Jung YU
发明人： Chen-Yi LEE , Chien-Ying YU , Chia-Jung YU
IPC分类号： H03K5/06
CPC分类号： H03L7/0997
摘要： A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.
摘要翻译：延迟单元包括第一反相晶体管对，第二反相晶体管对和多个延迟单元。第一反相晶体管对用于接收输入信号。第二反相晶体管对与第一反相晶体管对电交叉耦合并由第一反相晶体管对交叉控制。延迟单元在第一反相晶体管对之间和第二反向晶体管对之间级联，从而依次提供多个信号传播延迟，其中输入信号被第一反相晶体管对延迟预定时间，第二反相晶体管对和延迟单元，从而产生与预定时间对应的输出信号。提供了包括上述延迟单元的数字控制振荡器。

3. 发明授权

US07924100B2 Crystal-less communications device and self-calibrated clock generation method 有权
标题翻译：无水晶通信设备和自校准时钟生成方法
公开(公告)号：US07924100B2
公开(公告)日：2011-04-12
申请号：US12180176
申请日：2008-07-25
申请人： Chen-Yi Lee , Jui-Yuan Yu
发明人： Chen-Yi Lee , Jui-Yuan Yu
IPC分类号： G01R23/00
CPC分类号： H03J7/04
摘要： A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.
摘要翻译：通信设备使用本地时钟发生器从远程通信重新生成参考信号的载波频率。特别地，闭环用于自校准本地脉冲，直到频率固定在固定的频率范围内。一旦获得本地脉冲，解调器将使用本地脉冲来解调参考信号以产生数据信号。

4. 发明申请

US20100144121A1 Germanium FinFETs Having Dielectric Punch-Through Stoppers 有权
标题翻译：具有介质穿孔塞的锗FinFET
公开(公告)号：US20100144121A1
公开(公告)日：2010-06-10
申请号：US12329279
申请日：2008-12-05
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
IPC分类号： H01L21/20 , H01L21/28
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7851
摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
摘要翻译：形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

5. 发明申请

US20090037799A1 OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF 有权
标题翻译：适用于低密度奇偶校验（LDPC）解码器及其电路的操作方法
公开(公告)号：US20090037799A1
公开(公告)日：2009-02-05
申请号：US11939119
申请日：2007-11-13
申请人： Chih-Hao LIU , Yen-Chin Liao , Chen-Yi Lee , Hsie-Chia Chang , Yarsun Hsu
发明人： Chih-Hao LIU , Yen-Chin Liao , Chen-Yi Lee , Hsie-Chia Chang , Yarsun Hsu
IPC分类号： H03M13/47 , G06F11/00
CPC分类号： H03M13/1137 , H03M13/1114 , H03M13/658 , H03M13/6591
摘要： An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
摘要翻译：提出了一种应用于低密度奇偶校验（LDPC）解码器及其电路的操作方法，其中将原始比特节点并入校验节点以用于同时操作。根据新生成的检查消息和先前检查节点消息之间的不同，生成位节点消息。可以立即更新位节点消息，并且可以提高解码器吞吐量。另一方面，可以有效地减少LDPC解码器所需的存储器，并且也可以提高解码速度。

6. 发明申请

US20050289207A1 Fast fourier transform processor, dynamic scaling method and fast Fourier transform with radix-8 algorithm 审中-公开
标题翻译：快速傅里叶变换处理器，动态缩放方法和基数8算法的快速傅里叶变换
公开(公告)号：US20050289207A1
公开(公告)日：2005-12-29
申请号：US11052876
申请日：2005-02-09
申请人： Chen-Yi Lee , Yu-Wei Lin
发明人： Chen-Yi Lee , Yu-Wei Lin
IPC分类号： G06F15/00 , G06F17/14
CPC分类号： G06F17/142
摘要： The present invention provides a fast Fourier transform processor, dynamic scaling method and fast Fourier transform with radix-8 algorithm. It reduces quantization errors generated from the operation by using a matrix prefetch buffer-based fast Fourier transform processor. Operation sizes of the matrix prefetch buffer as block sizes the invention adjust the signals against overflow by the status of signals in each block. It can shunt time of complex multiplication operation systematically and reduce operation complexity in butterfly units by utilizing algorithms of 3-step radix-8 fast Fourier transform and re-scheduling. Moreover, the present invention provides a fast Fourier transform processor for realizing the methods and algorithms mentioned above.
摘要翻译：本发明提供了一种快速傅里叶变换处理器，动态缩放方法和使用radix-8算法的快速傅立叶变换。它通过使用基于矩阵预取缓冲器的快速傅里叶变换处理器来减少从操作产生的量化误差。作为块大小的矩阵预取缓冲器的操作大小本发明通过每个块中的信号的状态来调整信号与溢出。可以通过三步法-8快速傅立叶变换和重新调度的算法系统地分流复数乘法运算时间，降低蝴蝶单元的运算复杂度。此外，本发明提供一种用于实现上述方法和算法的快速傅里叶变换处理器。

7. 发明授权

US6150892A Method and device for digitally synthesizing frequency 失效
标题翻译：数字合成频率的方法和装置
公开(公告)号：US6150892A
公开(公告)日：2000-11-21
申请号：US182236
申请日：1998-10-30
申请人： Chen-Yi Lee , Terng-Yin Hsu , Bai-Jue Shieh , Chung Cheng Wang
发明人： Chen-Yi Lee , Terng-Yin Hsu , Bai-Jue Shieh , Chung Cheng Wang
IPC分类号： H03L7/085 , H03L7/095 , H03L7/099 , H03L7/18 , H03L7/00
CPC分类号： H03L7/0805 , H03L7/085 , H03L7/0997 , H03L7/18 , H03L2207/50 , H03L7/095
摘要： A method and device for frequency synthesizing, in which the digital frequency synthesizer includes a clock pair having two similar ring-oscillators to separately generate a search frequency and an output frequency, a frequency tracking unit, and a clock controlling unit. The frequency-search method includes two stages: one stage is the coarse search stage based on the "Prune-and-Search", and other stage is the fine search stage based on the "fixed-step" algorithm. In order to determine which search scheme is used to search the target frequency and to determine the lock status, two cost functions for search and lock-in are derived. These two cost functions define the search threshold and the lock threshold, and these thresholds define the cost window and the lock window. If the frequency error is higher than both the search and lock thresholds, a coarse search is activated to estimate the correct frequency. And only when the frequency error falls between the search and the lock thresholds, should the fine search be activated. By properly assigning these two thresholds, the search performance, such as tinting and frequency error, and the output resolution can be improved. The digital frequency synthesizer which can be designed at HDL level and synthesized as part of a target cell library.
摘要翻译：一种用于频率合成的方法和装置，其中数字频率合成器包括具有两个类似的环形振荡器以分别产生搜索频率和输出频率的时钟对，频率跟踪单元和时钟控制单元。频率搜索方法包括两个阶段：一阶段是基于“剪枝搜索”的粗搜索阶段，其他阶段是基于“固定步长”算法的精细搜索阶段。为了确定哪个搜索方案用于搜索目标频率并确定锁定状态，导出用于搜索和锁定的两个成本函数。这两个成本函数定义搜索阈值和锁定阈值，并且这些阈值定义了成本窗口和锁定窗口。如果频率误差高于搜索和锁定阈值，则会激活粗略搜索以估计正确的频率。只有当频率误差落在搜索和锁定阈值之间时，才能激活精细搜索。通过适当地分配这两个阈值，可以提高诸如着色和频率误差之类的搜索性能以及输出分辨率。数字频率合成器，可以在HDL级别设计，并作为目标单元库的一部分合成。

8. 发明授权

US5504919A Sorter structure based on shiftable content memory 失效
标题翻译：基于可移动内容记忆的分拣机结构
公开(公告)号：US5504919A
公开(公告)日：1996-04-02
申请号：US498108
申请日：1995-07-05
申请人： Chen-Yi Lee , Jer-Min Tsai , Po-Wen Hsieh
发明人： Chen-Yi Lee , Jer-Min Tsai , Po-Wen Hsieh
IPC分类号： G06F7/24 , G06F7/08
CPC分类号： G06F7/24 , Y10S707/99937
摘要： An optimized high-speed sorter has a plurality of process elements connected in series. Each process element includes a sorting unit used to store a sorted item, and a comparing/controlling unit coupled to the sorting unit. In this sorter, all sorted items are compared with the input item simultaneously, and then are divided into an LE-group wherein the sorted items are less than or equal to the input item, and a G-group wherein the sorted items are greater than the input item. We assume that the sorted items are arranged in a descending sequence from left to right. In the insertion operation, the sorted items in the LE-group are shifted rightwards simultaneously, and the input item is loaded in the position between the LE-group and G-group. In the deletion operation, only the sorted items in the LE-group are shifted leftwards simultaneously. In order to accelerate the operation speed, the sorter adopts a pre-shift strategy.
摘要翻译：优化的高速分选机具有串联连接的多个处理元件。每个处理单元包括用于存储分类项目的分类单元和耦合到分类单元的比较/控制单元。在该分拣机中，将所有排序的项目与输入项目同时进行比较，然后被划分为LE组，其中排序的项目小于或等于输入项目，以及G组，其中排序的项目大于输入项。我们假设排序的项目按照从左到右的降序排列。在插入操作中，LE组中的排序项目同时向右移动，并且输入项目被加载到LE组和G组之间的位置。在删除操作中，只有LE组中的排序项目同时向左移动。为了加快运营速度，分拣机采用了前转策略。

9. 发明申请

US20220297120A1 MICROFLUIDIC TEST SYSTEM AND MICROFLUIDIC TEST METHOD 有权
公开(公告)号：US20220297120A1
公开(公告)日：2022-09-22
申请号：US17695515
申请日：2022-03-15
申请人： Chen-Yi LEE
发明人： Chen-Yi LEE , Yun-Sheng CHAN
IPC分类号： B01L3/00
摘要： A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.

10. 发明授权

US08957477B2 Germanium FinFETs having dielectric punch-through stoppers 有权
标题翻译：锗FinFET具有绝缘穿孔塞
公开(公告)号：US08957477B2
公开(公告)日：2015-02-17
申请号：US13272994
申请日：2011-10-13
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
IPC分类号： H01L29/66 , H01L29/10 , H01L29/78 , H01L21/02
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7851
摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
摘要翻译：形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

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