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1. 发明申请

US20150095705A1 Instruction and Logic for Machine Checking Communication 有权
标题翻译：机器检查通信的指令和逻辑
公开(公告)号：US20150095705A1
公开(公告)日：2015-04-02
申请号：US14040092
申请日：2013-09-27
申请人： ASHOK RAJ , MOHAN J. KUMAR , JOSE A. VARGAS , WILLIAM G. AULD , CAMERON B. MCNAIRY , THEODROS YIGZAW , JAMES B. CROSSLAND , ANTHONY E. LUCK
发明人： ASHOK RAJ , MOHAN J. KUMAR , JOSE A. VARGAS , WILLIAM G. AULD , CAMERON B. MCNAIRY , THEODROS YIGZAW , JAMES B. CROSSLAND , ANTHONY E. LUCK
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0784 , G06F11/0793
摘要： A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.
摘要翻译：处理器包括用于确定在错误库中报告的错误状况的逻辑。错误组通信地耦合到处理器并且与处理器的逻辑处理器相关联。处理器包括产生指示错误状况的中断的另一逻辑。该处理器还包括用于选择性地将中断发送到与错误库相关联的单个逻辑处理器的另一逻辑。

2. 发明申请

US20150134932A1 STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：结构访问处理器，方法，系统和指令
公开(公告)号：US20150134932A1
公开(公告)日：2015-05-14
申请号：US13977152
申请日：2011-12-30
申请人： Cameron B. Mcnairy
发明人： Cameron B. Mcnairy
IPC分类号： G06F15/76 , G06F12/08
CPC分类号： G06F15/76 , G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/30105 , G06F9/3824 , G06F11/1064 , G06F12/0842 , G06F12/0846 , G06F12/0875 , G06F2015/765 , G06F2212/452
摘要： A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of the structure but are able to access one or more other portions of the structure. Non-architecturally visible data in the portion of the structure is modified, while the portion of the structure is in the sequestered state. The state of the portion of the structure is then changed from the sequestered state to a non-sequestered state, after the non-architecturally visible data in the portion of the structure has been modified. Other methods, apparatus, systems, and instructions are also disclosed.
摘要翻译：可以响应于一个或多个结构访问指令执行的方面的方法包括将处理器的结构的一部分的状态改变为隔离状态。在隔离状态下，处理器的组件不能访问结构的部分，但是能够访问结构的一个或多个其他部分。在结构部分中的非结构可视数据被修改，而结构的部分处于隔离状态。然后在结构部分中的非结构化可视数据已被修改之后，结构部分的状态从隔离状态改变为非隔离状态。还公开了其它方法，装置，系统和指令。

3. 发明授权

US09063855B2 Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based system 有权
标题翻译：在基于处理器的系统中采用令牌和源到目标范例来处理事务级别的故障处理
公开(公告)号：US09063855B2
公开(公告)日：2015-06-23
申请号：US13826843
申请日：2013-03-14
申请人： Cameron B. McNairy , Anil Agrawal , Jenna S. Mayfield , Eric A. Gouldey , Mark Millican
发明人： Cameron B. McNairy , Anil Agrawal , Jenna S. Mayfield , Eric A. Gouldey , Mark Millican
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10
CPC分类号： G06F11/0784 , G06F9/3836 , G06F9/3865 , G06F11/00 , G06F11/0724 , G06F11/10 , G06F11/1008 , G06F11/1024
摘要： A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.
摘要翻译：公开了一种用于检测处理装置中的错误的方法。处理装置的数据源单元与数据同步发送数据和限定符，限定符指示数据是不可校正的。处理装置中的至少一个中间功能单元接收数据和限定符。至少一个中间功能单元基于限定符检测数据是不可校正的。所述至少一个中间功能单元不将数据和限定符与数据同步地发送到处理设备的数据用户单元。数据用户单元接收数据和限定符。数据消费者单元根据限定符检测数据是不可校正的。数据消费者单位维护，不使用数据和限定词。

4. 发明授权

US07120755B2 Transfer of cache lines on-chip between processing cores in a multi-core system 有权
公开(公告)号：US07120755B2
公开(公告)日：2006-10-10
申请号：US10039060
申请日：2002-01-02
申请人： Sujat Jamil , Quinn W. Merrell , Cameron B. McNairy
发明人： Sujat Jamil , Quinn W. Merrell , Cameron B. McNairy
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.

5. 发明授权

US07100097B2 Detection of bit errors in maskable content addressable memories 有权
标题翻译：检测可屏蔽内容可寻址存储器中的位错误
公开(公告)号：US07100097B2
公开(公告)日：2006-08-29
申请号：US10196763
申请日：2002-07-16
申请人： Benjamin J. Patella , Ronny Lee Arnold , Cameron B. McNairy , Kevin David Safford
发明人： Benjamin J. Patella , Ronny Lee Arnold , Cameron B. McNairy , Kevin David Safford
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G06F12/1027 , G11C15/00
摘要： Parity and mask bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity and mask bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) and mask bit(s) stored at the address output by the CAM are output from the RAM. These reference parity bit(s) are compared to parity bit(s) generated from a query data value that is masked by the retrieved mask bit(s). In the absence of a CAM or RAM bit error, the reference parity bit(s) from the RAM and the parity bit(s) generated from the masked query data will match. If a CAM or RAM bit error occurred, these two sets of parity bit(s) will not match and thus an error will be detected. This error may be used as an indication that a false CAM match has occurred.
摘要翻译：奇偶校验和掩码位存储在耦合到CAM的随机存取存储器（RAM）中。该CAM可能是TLB的一部分。奇偶校验位和掩码位与CAM入口写入一起存储。在CAM查询匹配时，从RAM输出的地址处存储的参考奇偶校验位和掩码位从RAM输出。将这些参考奇偶校验位与从由检索的掩码位掩蔽的查询数据值生成的奇偶校验位进行比较。在没有CAM或RAM位错误的情况下，来自RAM的参考奇偶校验位和从掩蔽的查询数据生成的奇偶校验位将匹配。如果发生CAM或RAM位错误，则这两组奇偶校验位将不匹配，因此将检测到错误。该错误可以用作发生伪CAM匹配的指示。

6. 发明申请

US20140281747A1 Fault Handling at a Transaction Level by Employing a Token and a Source-to-Destination Paradigm in a Processor-Based System 有权
标题翻译：在基于处理器的系统中使用令牌和源到目的地范例的事务级别的故障处理
公开(公告)号：US20140281747A1
公开(公告)日：2014-09-18
申请号：US13826843
申请日：2013-03-14
申请人： Cameron B. McNairy , Anil Agrawal , Jenna S. Mayfield , Eric A. Gouldey , Mark Millican
发明人： Cameron B. McNairy , Anil Agrawal , Jenna S. Mayfield , Eric A. Gouldey , Mark Millican
IPC分类号： G06F11/07
CPC分类号： G06F11/0784 , G06F9/3836 , G06F9/3865 , G06F11/00 , G06F11/0724 , G06F11/10 , G06F11/1008 , G06F11/1024
摘要： A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.
摘要翻译：公开了一种用于检测处理装置中的错误的方法。处理装置的数据源单元与数据同步发送数据和限定符，限定符指示数据是不可校正的。处理装置中的至少一个中间功能单元接收数据和限定符。至少一个中间功能单元基于限定符检测数据是不可校正的。所述至少一个中间功能单元不将数据和限定符与数据同步地发送到处理设备的数据用户单元。数据用户单元接收数据和限定符。数据消费者单元根据限定符检测数据是不可校正的。数据消费者单位维护，不使用数据和限定词。

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