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1. 发明授权

US10791174B2 Mechanism for efficient discovery of storage resources in a rack scale architecture system 有权
公开(公告)号：US10791174B2
公开(公告)日：2020-09-29
申请号：US15221707
申请日：2016-07-28
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar
IPC分类号： H04L29/08 , H04L12/24
摘要： Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.

2. 发明申请

US20180288152A1 STORAGE DYNAMIC ACCESSIBILITY MECHANISM METHOD AND APPARATUS 审中-公开
公开(公告)号：US20180288152A1
公开(公告)日：2018-10-04
申请号：US15477065
申请日：2017-04-01
申请人： ANJANEYA R. CHAGAM REDDY , Mohan J. Kumar , Tushar Gohad
发明人： ANJANEYA R. CHAGAM REDDY , Mohan J. Kumar , Tushar Gohad
IPC分类号： H04L29/08 , G06F3/06
摘要： Apparatus and method for storage accessibility are disclosed herein. In some embodiments, a compute node may include one or more memories; and one or more processors in communication with the one or more memories, wherein the one or more processors include a module that is to select one or more particular storage devices of a plurality of storage devices distributed over the network in response to a data request made by an application that executes on the one or more processors, the one or more particular storage devices selected to fulfill the data request, and the module selects the one or more particular storage devices in accordance with a data object associated with the data request and one or more of current hardware operational state of respective storage devices of the plurality of storage devices and current performance characteristics of the respective storage devices of the plurality of storage devices.

3. 发明申请

US20180276137A1 APPARATUS AND METHOD FOR SYSTEM PHYSICAL ADDRESS TO MEMORY MODULE ADDRESS TRANSLATION 审中-公开
公开(公告)号：US20180276137A1
公开(公告)日：2018-09-27
申请号：US15465560
申请日：2017-03-21
申请人： ASHOK RAJ , SREENIVAS MANDAVA , SARATHY JAYAKUMAR , MOHAN J. KUMAR , THEODROS YIGZAW , RONALD N. STORY
发明人： ASHOK RAJ , SREENIVAS MANDAVA , SARATHY JAYAKUMAR , MOHAN J. KUMAR , THEODROS YIGZAW , RONALD N. STORY
IPC分类号： G06F12/1009 , G06F12/06 , G06F12/02 , G06F9/26
CPC分类号： G06F12/1009 , G06F9/268 , G06F9/3004 , G06F12/0215 , G06F12/0292 , G06F12/063 , G06F13/24 , G06F13/364 , G06F2212/65 , G06F2212/654
摘要： An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

4. 发明授权

US09612649B2 Method and apparatus to shutdown a memory channel 有权
公开(公告)号：US09612649B2
公开(公告)日：2017-04-04
申请号：US13997999
申请日：2011-12-22
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar
IPC分类号： G06F1/26 , G06F1/32 , G06F12/08 , G06F12/0804 , G06F12/0802 , G06F12/1027
CPC分类号： G06F1/3275 , G06F3/061 , G06F3/0625 , G06F3/0647 , G06F3/0685 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0888 , G06F12/1027 , G06F2212/1028 , G06F2212/1044 , G06F2212/2024 , G06F2212/205 , G06F2212/60 , Y02D10/13 , Y02D10/14
摘要： A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

5. 发明申请

US20160378697A1 PROVIDING DEDICATED RESOURCES FOR A SYSTEM MANAGEMENT MODE OF A PROCESSOR 审中-公开
标题翻译：为处理器的系统管理模式提供专用资源
公开(公告)号：US20160378697A1
公开(公告)日：2016-12-29
申请号：US14749893
申请日：2015-06-25
申请人： Sarathy Jayakumar , Ashok Raj , John G. Holm , Narayan Ranganathan , Mohan J. Kumar , Sergiu D. Ghetie
发明人： Sarathy Jayakumar , Ashok Raj , John G. Holm , Narayan Ranganathan , Mohan J. Kumar , Sergiu D. Ghetie
IPC分类号： G06F13/24 , G06F9/44 , G06F1/32
CPC分类号： G06F13/24 , G06F1/3228 , G06F1/3287 , G06F9/4405 , G06F9/4406 , Y02D10/171
摘要： In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心，其包括待保留用于在受保护的域中执行的第一核心，第一核心从操作系统隐藏。处理器还可以包括耦合到多个核的滤波器，其中滤波器包括多个场，每个场与多个核中的一个相关联，以指示受保护域的中断是否被引导到对应的核。描述和要求保护其他实施例。

6. 发明申请

US20160173465A1 TECHNOLOGIES FOR VERIFYING AUTHORIZED OPERATION OF SERVERS 审中-公开
标题翻译：验证服务器授权操作的技术
公开(公告)号：US20160173465A1
公开(公告)日：2016-06-16
申请号：US14568747
申请日：2014-12-12
申请人： Rajesh Poornachandran , Vincent J. Zimmer , Shahrok Shahidzadeh , Mohan J. Kumar , Sergiu D. Ghetie
发明人： Rajesh Poornachandran , Vincent J. Zimmer , Shahrok Shahidzadeh , Mohan J. Kumar , Sergiu D. Ghetie
IPC分类号： H04L29/06 , G06F21/44
CPC分类号： H04L63/107 , G06F21/34 , G06F21/575 , G06F2221/2111
摘要： Technologies for verifying authorized operation includes an administration server to query a dual-headed identification device of a server for identification data indicative of an identity of the server. The dual-headed identification device includes a wired communication circuit, a wireless communication circuit, and a memory having the identification data stored therein. The administration server further obtains the identification data from the dual-headed identification device of the server, determines a context of the server, and determines whether boot of the server is authorized based on the context of the server, the identification data of the server, and a security policy of the server.
摘要翻译：用于验证授权操作的技术包括管理服务器，用于查询服务器的双头标识设备，用于指示服务器的身份的标识数据。双头识别装置包括有线通信电路，无线通信电路和存储有识别数据的存储器。管理服务器还从服务器的双头识别装置获取识别数据，确定服务器的上下文，并根据服务器的上下文，服务器的识别数据，确定服务器的启动是否被授权，和服务器的安全策略。

7. 发明申请

US20150186278A1 RUNTIME PERSISTENCE 审中-公开
标题翻译：运行持续时间
公开(公告)号：US20150186278A1
公开(公告)日：2015-07-02
申请号：US14141255
申请日：2013-12-26
申请人： SARATHY JAYAKUMAR , MOHAN J. KUMAR , KRISHNAKANTH V. SISTLA
发明人： SARATHY JAYAKUMAR , MOHAN J. KUMAR , KRISHNAKANTH V. SISTLA
IPC分类号： G06F12/08 , G11C14/00 , G06F12/02
CPC分类号： G06F12/0804 , G06F1/3275 , G06F2212/202 , Y02D10/14
摘要： Apparatus, systems, and methods to manage memory operations are described. In one embodiment, a controller is coupled to a processor unit, and comprising logic to block additional transactions on the processor unit, initiate a cache flush to flush data from cache memory coupled to the processor unit to a memory controller buffer, block incoming data from the cache memory, and initiate a buffer flush to flush data from the memory controller buffer to a nonvolatile memory. Other examples are also disclosed and claimed.
摘要翻译：描述了管理存储器操作的装置，系统和方法。在一个实施例中，控制器耦合到处理器单元，并且包括用于阻止处理器单元上的附加事务的逻辑，启动高速缓冲存储器刷新以将耦合到处理器单元的高速缓冲存储器中的数据与存储器控制器缓冲器相冲突，缓冲存储器，并启动缓冲区刷新以将数据从存储器控制器缓冲区刷新到非易失性存储器。还公开并要求保护其他实例。

8. 发明申请

US20150186057A1 Data Coherency Model and Protocol at Cluster Level 有权
标题翻译：数据一致性模型和协议集群级别
公开(公告)号：US20150186057A1
公开(公告)日：2015-07-02
申请号：US14142733
申请日：2013-12-27
申请人： Debendra Das Sharma , Mohan J. Kumar , Balin T. Fleischer
发明人： Debendra Das Sharma , Mohan J. Kumar , Balin T. Fleischer
IPC分类号： G06F3/06 , G06F11/20 , G06F13/32
CPC分类号： G06F9/52 , G06F3/0619 , G06F3/0661 , G06F3/0688 , G06F9/467 , G06F11/2017 , G06F12/0815 , G06F12/0817 , G06F12/1081 , G06F13/1663 , G06F13/32 , G06F13/4022 , G06F2212/1056 , G11C14/009
摘要： An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
摘要翻译：这里描述了一种用于提供数据一致性的装置。该装置包括全局持久存储器。使用包含输入/输出（I / O）语义和内存语义的协议来访问全局永久存储器。该装置还包括反射存储区域。反射的存储器区域是全局持久存储器的一部分，并且多个节点的每个节点将反射的存储器区域映射到不可高速缓存的空间中。此外，该装置包括信号量存储器。信号量存储器为强制数据一致性提供硬件辅助。

9. 发明授权

US08832457B2 Methods and apparatus for authenticating components of processing systems 有权
标题翻译：用于认证处理系统组件的方法和装置
公开(公告)号：US08832457B2
公开(公告)日：2014-09-09
申请号：US13532334
申请日：2012-06-25
申请人： Mohan J. Kumar , Shay Gueron
发明人： Mohan J. Kumar , Shay Gueron
IPC分类号： G06F21/00 , G06F21/57
CPC分类号： G06F21/57 , G06F21/575 , G06F2221/2129
摘要： When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed.
摘要翻译：当处理系统引导时，它可以从非易失性存储器检索加密密钥的加密版本到处理单元，该处理单元可以解密密码密钥。处理系统还可以检索用于处理系统的软件的预定认证码，并且处理系统可以使用密码密钥来计算软件的当前认证码。然后，处理系统可以通过将预定认证码与当前认证码进行比较来确定软件是否应该被信任。在各种实施例中，处理单元可以使用存储在处理单元的非易失性存储器中的密钥对加密密钥的加密版本进行解密，散列消息认证码（HMAC）可以用作认证码，和/或软件被认证可以是启动固件，虚拟机监视器（VMM）或其他软件。描述和要求保护其他实施例。

10. 发明申请

US20140195876A1 Memory Module Architecture 有权
标题翻译：内存模块架构
公开(公告)号：US20140195876A1
公开(公告)日：2014-07-10
申请号：US13993506
申请日：2011-12-28
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Debaleena Das , Dimitrios Ziakas
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Debaleena Das , Dimitrios Ziakas
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/1064 , G11C5/04 , G11C13/0004
摘要： In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.
摘要翻译：根据一些实施例，可以组织包含相变存储器元件的存储器模块，使得每个存储器集成电路都包括数据和纠错码。作为在每个集成电路中包括纠错码的结果，可以避免存储器模块提取错误校正码的额外访问，从而在一些实施例中提高整个存储器模块的性能。

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