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1. 发明授权

US06377492B1 Memory architecture for read and write at the same time using a conventional cell 有权
标题翻译：使用传统单元同时进行读写的内存架构
公开(公告)号：US06377492B1
公开(公告)日：2002-04-23
申请号：US09809839
申请日：2001-03-19
申请人： Bor-Doou Rong , Ghy-Bin Wang
发明人： Bor-Doou Rong , Ghy-Bin Wang
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/18 , G11C8/16
摘要： A simultaneous read and write memory is shown. The memory is configured into a plurality of sections. Connected to each section is a wordline multiplexer which is used to select a wordline for reading or writing. A write wordline decoder and a read wordline decoder are each connected to all the wordline multiplexers. The multiplexers choose either a write wordline or a read wordline independently for each memory section. A write data path and a read data path are separately connected to each of the memory sections. With the separate write and read wordline addressing and the separate data paths for reading and writing, one section can be written simultaneous to the reading from a second section.
摘要翻译：显示同时的读写存储器。存储器被配置成多个部分。连接到每个部分是字线多路复用器，用于选择用于读取或写入的字线。写字字解码器和读字字解码器各自连接到所有字线复用器。多路复用器为每个存储器部分独立地选择写字线或读字线。写入数据路径和读取数据路径分别连接到每个存储器部分。通过单独的写入和读取字线寻址以及用于读取和写入的单独数据路径，可以将一个部分与第二个部分的读取同时写入。

2. 发明授权

US07551806B2 Two stage interpolation apparatus and method for up-scaling an image on display device 有权
标题翻译：用于在显示装置上对图像进行放大的两级插值装置和方法
公开(公告)号：US07551806B2
公开(公告)日：2009-06-23
申请号：US11191762
申请日：2005-07-28
申请人： Ghy-Bin Wang , Ming-Sung Huang , Inn Shing Liu
发明人： Ghy-Bin Wang , Ming-Sung Huang , Inn Shing Liu
IPC分类号： G06K9/32 , G06F15/00 , H04N1/46
CPC分类号： G06T3/4007
摘要： A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.
摘要翻译：图形显示适配器具有连接用于接收以第一时钟速率同步的源像素数据并以第二时钟速率内插行的像素组的行内插器电路。行内插存储装置以第二时钟速率接收并保持每行的内插源像素数据。列插值器电路以第三时钟速率提取内插源像素数据。然后，列插值器电路以第三时钟速率内插内插源像素数据的分组，并发送用于显示的目的地图形像素数据。第二个时钟速率可能等于第一个时钟速率或第一个和第三个时钟速率的速度。

3. 发明申请

US20070025644A1 Two stage interpolation apparatus and method for up-scaling an image on display device 有权
标题翻译：用于在显示装置上对图像进行放大的两级插值装置和方法
公开(公告)号：US20070025644A1
公开(公告)日：2007-02-01
申请号：US11191762
申请日：2005-07-28
申请人： Ghy-Bin Wang , Ming-Sung Huang , Inn Liu
发明人： Ghy-Bin Wang , Ming-Sung Huang , Inn Liu
IPC分类号： G06K9/32
CPC分类号： G06T3/4007
摘要： A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.
摘要翻译：图形显示适配器具有连接用于接收以第一时钟速率同步的源像素数据并以第二时钟速率内插行的像素组的行内插器电路。行内插存储装置以第二时钟速率接收并保持每行的内插源像素数据。列插值器电路以第三时钟速率提取内插源像素数据。然后，列插值器电路以第三时钟速率内插内插源像素数据的分组，并发送用于显示的目的地图形像素数据。第二个时钟速率可能等于第一个时钟速率或第一个和第三个时钟速率的速度。

4. 发明申请

US20070257877A1 Method and circuit for transferring data stream across multiple clock domains 有权
标题翻译：用于跨多个时钟域传输数据流的方法和电路
公开(公告)号：US20070257877A1
公开(公告)日：2007-11-08
申请号：US11402800
申请日：2006-04-13
申请人： Ghy-Bin Wang , Hsien-Sheng Huang
发明人： Ghy-Bin Wang , Hsien-Sheng Huang
IPC分类号： G09G3/36 , H04L7/00
CPC分类号： H04L7/00 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , H04L7/0045 , H04L7/005
摘要： The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream and a sampling module sequentially samples and outputs each signal in the first group signals and the second group signals by the N sampling pulses with a sequence.
摘要翻译：该方法和电路提供了一个有效的实现来处理多个时钟域之间的数据传输问题。移位电路移动输入数据流，并且采样模块通过具有序列的N个采样脉冲顺序采样并输出第一组信号和第二组信号中的每个信号。

5. 发明授权

US5708688A High speed programmable burst address generation circuit 失效
标题翻译：高速可编程突发地址产生电路
公开(公告)号：US5708688A
公开(公告)日：1998-01-13
申请号：US652213
申请日：1996-05-23
申请人： Tah-Kang Joseph Ting , Ghy-Bin Wang , Jeng-Tzong Shih
发明人： Tah-Kang Joseph Ting , Ghy-Bin Wang , Jeng-Tzong Shih
IPC分类号： G11C7/10 , H03K23/66 , H03K21/40
CPC分类号： H03K23/66 , G11C7/1018
摘要： A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.
摘要翻译：描述可编程突发序列计数器。该计数器能够从呈现给计数器的输入的初始二进制数开始，对线性突发序列或交织突发序列中的二进制数的序列进行计数。可编程突发序列计数器可用于生成用于从存储器阵列存储和检索数字数据的地址。

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