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1. 发明授权

US06653709B2 CMOS output circuit with enhanced ESD protection using drain side implantation 有权
公开(公告)号：US06653709B2
公开(公告)日：2003-11-25
申请号：US10213612
申请日：2002-08-07
申请人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
发明人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
IPC分类号： H01L2972
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/0266
摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

2. 发明授权

US06207479B1 Place and route method for integrated circuit design 有权
标题翻译：集成电路设计的放置和布线方法
公开(公告)号：US06207479B1
公开(公告)日：2001-03-27
申请号：US09332127
申请日：1999-06-14
申请人： Boon-Khim Liew , Jing-Meng Liu
发明人： Boon-Khim Liew , Jing-Meng Liu
IPC分类号： H01L2182
CPC分类号： H01L27/118 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of placing and routing metal wires for integrated circuit. In the method, a grid pattern is constructed by a plurality of floors with metal wires The grid size is set to be equal to a metal pitch. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and the forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor corners. Furthermore, the connection cells is constructed and placed in a defined via site for connecting the metal wires in individually floor.
摘要翻译：本发明提供了一种用于集成电路放置和布线金属线的方法。在该方法中，网格图案由具有金属线的多个楼层构成。网格尺寸被设定为等于金属间距。然而，放置在网格图案中的每个通道必须受到棋盘样图案的约束。类似棋盘的模式包括通过站点和禁止站点的潜在可能性，其中通过站点和禁止站点的潜在位置彼此干预，使得网格中的每个潜在通过站点在其最近的相邻角落处禁止站点。此外，连接单元被构造并放置在限定的通孔位置中，用于将金属线连接在单独的地板中。

3. 发明授权

US06444511B1 CMOS output circuit with enhanced ESD protection using drain side implantation 有权
标题翻译： CMOS输出电路采用漏极侧注入增强ESD保护
公开(公告)号：US06444511B1
公开(公告)日：2002-09-03
申请号：US09867562
申请日：2001-05-31
申请人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
发明人： Yi-Hsu Wu , Hung-Der Su , Jian-Hsing Lee , Boon-Khim Liew
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/0266
摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.
摘要翻译：实现了具有增强ESD保护的新型级联NMOS晶体管输出电路。驱动器PMOS晶体管的源极连接到电源，栅极连接到输入信号，漏极连接到输出焊盘。虚设PMOS晶体管的源极和栅极连接到电源，漏极连接到输出焊盘。驱动器NMOS级联堆叠包括第一和第二NMOS晶体管。第一个NMOS晶体管的源极连接到地，栅极连接到输入信号。第二个NMOS晶体管的栅极连接到电源，源极连接到第一个NMOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。虚设NMOS级联堆叠包括第三和第四NMOS晶体管。第三个NMOS晶体管的栅极和源极接地。第四个NMOS晶体管的栅极连接到电源，源极连接到第三个MOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。

4. 发明授权

US06174754B1 Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors 有权
标题翻译：用于形成绝缘体上硅（SOI）和绝缘体源/绝缘体（SDOI）晶体管的方法
公开(公告)号：US06174754B1
公开(公告)日：2001-01-16
申请号：US09527608
申请日：2000-03-17
申请人： Jin-Yuan Lee , Mong-Song Liang , Boon-Khim Liew
发明人： Jin-Yuan Lee , Mong-Song Liang , Boon-Khim Liew
IPC分类号： H01L21335
CPC分类号： H01L29/66651 , H01L21/76264 , H01L21/76272 , H01L21/76283 , H01L29/0653
摘要： A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is patterned to define hole/channel regions having predetermined widths. An amorphous silicon layer is formed having a predetermined thickness over the dielectric layer and the hole/channel regions, filling the hole/channel regions. Heating (grain growth) the amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over the dielectric layer and through the hole/channel regions, filling the hole/channel regions. The planar silicon layer is patterned to expose the hole/channel regions and define transistor regions. Trenches are formed in the silicon surface adjacent the transistor regions. Shallow trench isolation regions are formed filling the trenches and having a predetermined depth. Transistor structures are formed within the transistor regions, separated by the shallow trench isolation regions.
摘要翻译：一种在半导体衬底上制造晶体管器件的方法，包括以下步骤。提供了具有覆盖绝缘介电层的硅表面的半导体衬底。图案化绝缘电介质层以限定具有预定宽度的孔/沟道区域。在电介质层和孔/沟道区域上形成具有预定厚度的非晶硅层，填充孔/沟道区域。加热（晶粒生长）非晶硅层，以形成平坦的硅层，其包含至少一部分具有预定厚度的外延硅，在电介质层上并穿过孔/沟道区，填充孔/沟道区。图案化平面硅层以暴露空穴/沟道区域并限定晶体管区域。沟槽形成在与晶体管区域相邻的硅表面中。形成了填充沟槽并具有预定深度的浅沟槽隔离区。在晶体管区域内形成晶体管结构，由浅沟槽隔离区分开。

5. 发明授权

US6117737A Reduction of a hot carrier effect by an additional furnace anneal increasing transient enhanced diffusion for devices comprised with low temperature spacers 有权
标题翻译：通过额外的炉退火来减少热载流子效应，增加了由低温间隔物组成的器件的瞬时增强的扩散
公开(公告)号：US6117737A
公开(公告)日：2000-09-12
申请号：US246895
申请日：1999-02-08
申请人： Jyh-Haur Wang , Boon-Khim Liew
发明人： Jyh-Haur Wang , Boon-Khim Liew
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418
摘要： A process for fabricating an I/O device, comprised with an LDD source/drain region, featuring a graded dopant profile, and simultaneously fabricating a core device, comprised with an LDD source/drain region, featuring a sharp dopant profile, has been developed. The process features the initial creation of the I/O device, LDD source/drain region, via an ion implantation procedure, followed by a furnace anneal procedure, to initiate transient enhanced diffusion, resulting in a graded dopant profile, for the I/O device, LDD source/drain region. The graded dopant profile, affords reduced risk of hot carrier effects, prevalent with the higher voltage, I/O devices. The creation of the core device, LDD source/drain region, is next addressed via another ion implantation, followed by a RTA procedure, used to activate the implanted species, and to create an LDD source/drain region, for the core device, featuring a sharp dopant profile, needed for performance objectives. The creation of insulator spacers, on the sides of the gate structures, is followed by the formation of heavily doped source/drain regions, for both I/O, and core devices.
摘要翻译：已经开发了一种制造I / O装置的方法，该装置包括LDD源极/漏极区域，其特征在于具有渐变的掺杂剂分布，并且同时制造包含具有尖锐掺杂剂分布的LDD源极/漏极区域的核心器件。该过程的特征在于通过离子注入程序初始创建I / O设备，LDD源极/漏极区，随后进行炉退火程序，以启动瞬态增强扩散，从而产生等级掺杂剂分布，用于I / O 器件，LDD源极/漏极区域。分级掺杂剂分布，降低了热载流子效应的风险，与较高电压I / O器件一样普遍。核心器件LDD源极/漏极区域的产生接下来通过另一个离子注入来处理，随后是用于激活注入物质的RTA程序，并为核心器件产生LDD源极/漏极区域，其特征在于性能目标所需的尖锐掺杂剂轮廓。在栅极结构的侧面上形成绝缘体间隔物之后，为I / O和核心器件形成重掺杂的源极/漏极区域。

6. 发明申请

US20130020640A1 SEMICONDUCTOR DEVICE STRUCTURE INSULATED FROM A BULK SILICON SUBSTRATE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：从大块硅基板绝缘的半导体器件结构及其形成方法
公开(公告)号：US20130020640A1
公开(公告)日：2013-01-24
申请号：US13185373
申请日：2011-07-18
申请人： John Y. CHEN , Boon-Khim Liew
发明人： John Y. CHEN , Boon-Khim Liew
IPC分类号： H01L29/772 , H01L21/31
CPC分类号： H01L21/76205 , H01L29/66795 , H01L29/785
摘要： A structure making up a part of a semiconductor device, such as a fin structure of a finFET device, is formed on and electrically isolated from a semiconductor substrate. The structure is comprised of the semiconductor substrate material and is electrically isolated from a remaining portion of the semiconductor substrate by an insulating barrier. The insulating barrier is formed by an isotropic oxidation process that oxidizes portions of the semiconductor substrate that are not protected by an oxidation barrier.
摘要翻译：构成半导体器件的一部分的结构，例如finFET器件的鳍结构，形成在半导体衬底上并与之电绝缘。该结构由半导体衬底材料组成并且通过绝缘屏障与半导体衬底的剩余部分电隔离。绝缘屏障是通过各向同性的氧化工艺形成的，该方法氧化未被氧化屏障保护的半导体衬底的部分。

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