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1. 发明申请

US20130141979A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20130141979A1
公开(公告)日：2013-06-06
申请号：US13599997
申请日：2012-08-30
申请人： Bo Kyeom KIM
发明人： Bo Kyeom KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/06 , G11C16/26
摘要： A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
摘要翻译：一种半导体存储装置，包括锁存单元，配置为响应于复位选择信号的激活而被驱动并且重置第一节点和第二节点; 以及辅助驱动单元，被配置为响应于所述复位选择信号和所述第一节点或所述第二节点的电压逻辑电平来支持所述锁存单元的驱动力，其中所述第一节点和所述第二节点具有基本相反的电压逻辑电平。

2. 发明授权

US08060813B2 Apparatus and method for generating error detection codes 有权
标题翻译：用于产生错误检测码的装置和方法
公开(公告)号：US08060813B2
公开(公告)日：2011-11-15
申请号：US11958324
申请日：2007-12-17
申请人： Sang Sic Yoon , Bo Kyeom Kim
发明人： Sang Sic Yoon , Bo Kyeom Kim
IPC分类号： G06F11/10
CPC分类号： G06F11/1004
摘要： An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.
摘要翻译：用于生成错误检测码的装置可以包括：错误检测码生成单元，被配置为使用虚拟DBI信息和数据生成虚拟错误检测码;以及错误检测码再现单元，被配置为使用定义了偶数和奇数信息来生成错误检测码与生成错误检测码相关联的数据的数量是偶数还是奇数，与偶数和奇数信息相关联的DBI信息以及虚拟错误检测码。

3. 发明申请

US20090273381A1 DELAYED LOCKED LOOP CIRCUIT 失效
标题翻译：延迟锁定环路
公开(公告)号：US20090273381A1
公开(公告)日：2009-11-05
申请号：US12164199
申请日：2008-06-30
申请人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
发明人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/087 , H03L7/091 , H03L7/093
摘要： A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.
摘要翻译：用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟之一作为存储器件的内部时钟。

4. 发明授权

US09230668B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US09230668B2
公开(公告)日：2016-01-05
申请号：US13599997
申请日：2012-08-30
申请人： Bo Kyeom Kim
发明人： Bo Kyeom Kim
IPC分类号： G11C11/34 , G11C16/26 , G11C16/06
CPC分类号： G11C16/06 , G11C16/26
摘要： A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
摘要翻译：一种半导体存储装置，包括锁存单元，配置为响应于复位选择信号的激活而被驱动并且重置第一节点和第二节点; 以及辅助驱动单元，被配置为响应于所述复位选择信号和所述第一节点或所述第二节点的电压逻辑电平来支持所述锁存单元的驱动力，其中所述第一节点和所述第二节点具有基本相反的电压逻辑电平。

5. 发明申请

US20130315013A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20130315013A1
公开(公告)日：2013-11-28
申请号：US13609499
申请日：2012-09-11
申请人： Bo-Kyeom Kim
发明人： Bo-Kyeom Kim
IPC分类号： G11C7/10
CPC分类号： G11C29/808 , G11C7/1039
摘要： A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
摘要翻译：存储器件包括：第一主页缓冲器阵列，被配置为访问第一主存储器阵列的数据; 配置为访问第二主存储器阵列的数据的第二主页缓冲器阵列; 冗余页缓冲器阵列，被配置为访问代替所述第一和第二主存储器阵列的冗余存储器阵列的数据; 第一冗余传送单元，被配置为当第一列地址指示第一主存储器阵列的一个或多个缺陷列时，通过第一冗余总线在冗余页缓冲器阵列和存储器件外部之间传送数据; 以及第二冗余传送单元，被配置为当第二列地址指示第二主存储器阵列的一个或多个有缺陷的列时，通过第二冗余总线在冗余页缓冲器阵列和外部之间传送数据。

6. 发明申请

US20090019344A1 APPARATUS AND METHOD FOR GENERATING ERROR DETECTION CODES 有权
标题翻译：用于产生错误检测代码的装置和方法
公开(公告)号：US20090019344A1
公开(公告)日：2009-01-15
申请号：US11958324
申请日：2007-12-17
申请人： Sang Sic Yoon , Bo Kyeom Kim
发明人： Sang Sic Yoon , Bo Kyeom Kim
IPC分类号： G06F11/10
CPC分类号： G06F11/1004
摘要： An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.
摘要翻译：用于生成错误检测码的装置可以包括：错误检测码生成单元，被配置为使用虚拟DBI信息和数据生成虚拟错误检测码;以及错误检测码再现单元，被配置为使用定义了偶数和奇数信息来生成错误检测码与生成错误检测码相关联的数据的数量是偶数还是奇数，与偶数和奇数信息相关联的DBI信息以及虚拟错误检测码。

7. 发明授权

US09190176B2 Memory device with redundancy page buffer array 有权
标题翻译：具有冗余页面缓冲区数组的内存设备
公开(公告)号：US09190176B2
公开(公告)日：2015-11-17
申请号：US13609499
申请日：2012-09-11
申请人： Bo-Kyeom Kim
发明人： Bo-Kyeom Kim
IPC分类号： G11C29/00 , G11C7/10
CPC分类号： G11C29/808 , G11C7/1039
摘要： A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
摘要翻译：存储器件包括：第一主页缓冲器阵列，被配置为访问第一主存储器阵列的数据; 配置为访问第二主存储器阵列的数据的第二主页缓冲器阵列; 冗余页缓冲器阵列，被配置为访问代替所述第一和第二主存储器阵列的冗余存储器阵列的数据; 第一冗余传送单元，被配置为当第一列地址指示第一主存储器阵列的一个或多个缺陷列时，通过第一冗余总线在冗余页缓冲器阵列和存储器件外部之间传送数据; 以及第二冗余传送单元，被配置为当第二列地址指示第二主存储器阵列的一个或多个有缺陷的列时，通过第二冗余总线在冗余页缓冲器阵列和外部之间传送数据。

8. 发明授权

US08065550B2 Digital delay locked loop circuit using mode register set 有权
标题翻译：使用模式寄存器组的数字延迟锁定环路电路
公开(公告)号：US08065550B2
公开(公告)日：2011-11-22
申请号：US12005917
申请日：2007-12-28
申请人： Bo-Kyeom Kim , Sang-Sik Yoon
发明人： Bo-Kyeom Kim , Sang-Sik Yoon
IPC分类号： G06F1/04
CPC分类号： G06F1/12 , G06F11/1008
摘要： A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
摘要翻译：半导体存储器件包括用于建立关于延迟时间的信息的模式寄存器组，用于基于系统时钟的单位周期计算数据时钟的I / O路径延迟时间的延迟时间计算器和延迟锁定时钟发生器，用于在数据时钟中反映从在模式寄存器组中建立的信息中减去延迟时间计算器的输出的值。

9. 发明授权

US07940576B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07940576B2
公开(公告)日：2011-05-10
申请号：US12323687
申请日：2008-11-26
申请人： Bo-Kyeom Kim , Sang-Sic Yoon
发明人： Bo-Kyeom Kim , Sang-Sic Yoon
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1084 , G11C7/1096 , G11C8/06 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4096
摘要： There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.
摘要翻译：提供了一种半导体存储器件，包括：多个银行组，每个组包括多个存储体; 多个用于接收银行组的数据的预定数量的数据焊盘，其中数据焊盘被分成多个接收数据的第一焊盘组和根据数据输入/输出有选择地接收数据的多个第二焊盘组期权价值第一驱动单元，被配置为驱动经由所述第一焊盘组输入的数据，以将经由所述第一焊盘组输入的数据传送到对应于所述第一焊盘组的所述存储体组; 第二驱动单元，被配置为驱动经由所述第二焊盘组输入的数据，以将经由所述第二焊盘组输入的数据传送到对应于所述第二焊盘组的所述存储体组; 以及第三驱动单元，被配置为响应于所述数据输入/输出选项值，经由所述第一焊盘组驱动经由所述第一焊盘组输入的数据到与所述第二焊盘组对应的所述存储体组。

10. 发明申请

US20090273990A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090273990A1
公开(公告)日：2009-11-05
申请号：US12323687
申请日：2008-11-26
申请人： Bo-Kyeom KIM , Sang-Sic YOON
发明人： Bo-Kyeom KIM , Sang-Sic YOON
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1084 , G11C7/1096 , G11C8/06 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4096
摘要： There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.
摘要翻译：提供了一种半导体存储器件，包括：多个银行组，每个组包括多个存储体; 多个用于接收银行组的数据的预定数量的数据焊盘，其中数据焊盘被分成多个接收数据的第一焊盘组和根据数据输入/输出有选择地接收数据的多个第二焊盘组期权价值第一驱动单元，被配置为驱动经由所述第一焊盘组输入的数据，以将经由所述第一焊盘组输入的数据传送到对应于所述第一焊盘组的所述存储体组; 第二驱动单元，被配置为驱动经由所述第二焊盘组输入的数据，以将经由所述第二焊盘组输入的数据传送到对应于所述第二焊盘组的所述存储体组; 以及第三驱动单元，被配置为响应于所述数据输入/输出选项值，经由所述第一焊盘组驱动经由所述第一焊盘组输入的数据到与所述第二焊盘组对应的所述存储体组。

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