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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090273990A1
    • 2009-11-05
    • US12323687
    • 2008-11-26
    • Bo-Kyeom KIMSang-Sic YOON
    • Bo-Kyeom KIMSang-Sic YOON
    • G11C7/00G11C8/00
    • G11C7/1078G11C7/1039G11C7/1084G11C7/1096G11C8/06G11C8/12G11C11/408G11C11/4093G11C11/4096
    • There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.
    • 提供了一种半导体存储器件,包括:多个银行组,每个组包括多个存储体; 多个用于接收银行组的数据的预定数量的数据焊盘,其中数据焊盘被分成多个接收数据的第一焊盘组和根据数据输入/输出有选择地接收数据的多个第二焊盘组 期权价值 第一驱动单元,被配置为驱动经由所述第一焊盘组输入的数据,以将经由所述第一焊盘组输入的数据传送到对应于所述第一焊盘组的所述存储体组; 第二驱动单元,被配置为驱动经由所述第二焊盘组输入的数据,以将经由所述第二焊盘组输入的数据传送到对应于所述第二焊盘组的所述存储体组; 以及第三驱动单元,被配置为响应于所述数据输入/输出选项值,经由所述第一焊盘组驱动经由所述第一焊盘组输入的数据到与所述第二焊盘组对应的所述存储体组。
    • 2. 发明申请
    • SEMICONDUCTOR INTERATED CIRCUIT
    • 半导体相关电路
    • US20130027121A1
    • 2013-01-31
    • US13411727
    • 2012-03-05
    • Sang-Sic YOON
    • Sang-Sic YOON
    • G05F1/10
    • G05F1/56G11C5/147
    • A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.
    • 半导体集成电路包括:被配置为接收第一电压的第一焊盘,被配置为接收第二电压的第二焊盘;内部电压产生电路,被配置为响应于所述第二电压产生具有与所述第一电压相同的电压电平的第三电压 测试模式期间的电压以及在正常模式期间使用第一电压和第二电压进行正常操作的内部电路,并且在测试模式期间使用第二电压和第三电压进行测试操作。