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1. 发明授权

US08065550B2 Digital delay locked loop circuit using mode register set 有权
标题翻译：使用模式寄存器组的数字延迟锁定环路电路
公开(公告)号：US08065550B2
公开(公告)日：2011-11-22
申请号：US12005917
申请日：2007-12-28
申请人： Bo-Kyeom Kim , Sang-Sik Yoon
发明人： Bo-Kyeom Kim , Sang-Sik Yoon
IPC分类号： G06F1/04
CPC分类号： G06F1/12 , G06F11/1008
摘要： A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
摘要翻译：半导体存储器件包括用于建立关于延迟时间的信息的模式寄存器组，用于基于系统时钟的单位周期计算数据时钟的I / O路径延迟时间的延迟时间计算器和延迟锁定时钟发生器，用于在数据时钟中反映从在模式寄存器组中建立的信息中减去延迟时间计算器的输出的值。

2. 发明申请

US20090119533A1 Digital delay locked loop circuit using mode register set 有权
标题翻译：使用模式寄存器组的数字延迟锁定环路电路
公开(公告)号：US20090119533A1
公开(公告)日：2009-05-07
申请号：US12005917
申请日：2007-12-28
申请人： Bo-Kyeom Kim , Sang-Sik Yoon
发明人： Bo-Kyeom Kim , Sang-Sik Yoon
IPC分类号： G06F1/12 , G06F1/08 , G06F11/07
CPC分类号： G06F1/12 , G06F11/1008
摘要： A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
摘要翻译：半导体存储器件包括用于建立关于延迟时间的信息的模式寄存器组，用于基于系统时钟的单位周期计算数据时钟的I / O路径延迟时间的延迟时间计算器和延迟锁定时钟发生器，用于在数据时钟中反映从在模式寄存器组中建立的信息中减去延迟时间计算器的输出的值。

3. 发明申请

US20090273381A1 DELAYED LOCKED LOOP CIRCUIT 失效
标题翻译：延迟锁定环路
公开(公告)号：US20090273381A1
公开(公告)日：2009-11-05
申请号：US12164199
申请日：2008-06-30
申请人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
发明人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/087 , H03L7/091 , H03L7/093
摘要： A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.
摘要翻译：用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟之一作为存储器件的内部时钟。

4. 发明申请

US20130315013A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20130315013A1
公开(公告)日：2013-11-28
申请号：US13609499
申请日：2012-09-11
申请人： Bo-Kyeom Kim
发明人： Bo-Kyeom Kim
IPC分类号： G11C7/10
CPC分类号： G11C29/808 , G11C7/1039
摘要： A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
摘要翻译：存储器件包括：第一主页缓冲器阵列，被配置为访问第一主存储器阵列的数据; 配置为访问第二主存储器阵列的数据的第二主页缓冲器阵列; 冗余页缓冲器阵列，被配置为访问代替所述第一和第二主存储器阵列的冗余存储器阵列的数据; 第一冗余传送单元，被配置为当第一列地址指示第一主存储器阵列的一个或多个缺陷列时，通过第一冗余总线在冗余页缓冲器阵列和存储器件外部之间传送数据; 以及第二冗余传送单元，被配置为当第二列地址指示第二主存储器阵列的一个或多个有缺陷的列时，通过第二冗余总线在冗余页缓冲器阵列和外部之间传送数据。

5. 发明授权

US08000166B2 Semiconductor memory device and operating method thereof 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08000166B2
公开(公告)日：2011-08-16
申请号：US12277609
申请日：2008-11-25
申请人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
发明人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
IPC分类号： G11C8/18
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C7/225
摘要： A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.
摘要翻译：一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元响应于第一和第二时钟传输线的输出时钟。

6. 发明申请

US20090284293A1 DUTY CORRECTION CIRCUIT 有权
标题翻译：占空比校正电路
公开(公告)号：US20090284293A1
公开(公告)日：2009-11-19
申请号：US12343753
申请日：2008-12-24
申请人： Kyung-Hoon Kim , Bo-Kyeom Kim
发明人： Kyung-Hoon Kim , Bo-Kyeom Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00065
摘要： A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.
摘要翻译：占空比校正电路包括占空比传感器，用于通过感测速度控制信号控制占空比感测速度，并通过感测时钟的占空比来输出校正信号;以及占空比校正器，用于控制时钟的占空比响应于校正信号。

7. 发明授权

US07800423B2 Duty correction circuit 有权
标题翻译：负责校正电路
公开(公告)号：US07800423B2
公开(公告)日：2010-09-21
申请号：US12343753
申请日：2008-12-24
申请人： Kyung-Hoon Kim , Bo-Kyeom Kim
发明人： Kyung-Hoon Kim , Bo-Kyeom Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00065
摘要： A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.
摘要翻译：占空比校正电路包括占空比传感器，用于通过感测速度控制信号控制占空比感测速度，并通过感测时钟的占空比来输出校正信号;以及占空比校正器，用于控制时钟的占空比响应于校正信号。

8. 发明授权

US07710171B2 Delayed locked loop circuit 失效
标题翻译：延迟锁定回路电路
公开(公告)号：US07710171B2
公开(公告)日：2010-05-04
申请号：US12164199
申请日：2008-06-30
申请人： Kyung-Hoon Kim , Bo-Kyeom Kim , Taek-Sang Song
发明人： Kyung-Hoon Kim , Bo-Kyeom Kim , Taek-Sang Song
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/087 , H03L7/091 , H03L7/093
摘要： A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.
摘要翻译：用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟中的一个作为存储器件的内部时钟。

9. 发明申请

US20090323444A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 失效
标题翻译：半导体存储器件及其工作方法
公开(公告)号：US20090323444A1
公开(公告)日：2009-12-31
申请号：US12277609
申请日：2008-11-25
申请人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
发明人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
IPC分类号： G11C7/22
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C7/225
摘要： A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.
摘要翻译：一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元响应于第一和第二时钟传输线的输出时钟。

10. 发明授权

US09190176B2 Memory device with redundancy page buffer array 有权
标题翻译：具有冗余页面缓冲区数组的内存设备
公开(公告)号：US09190176B2
公开(公告)日：2015-11-17
申请号：US13609499
申请日：2012-09-11
申请人： Bo-Kyeom Kim
发明人： Bo-Kyeom Kim
IPC分类号： G11C29/00 , G11C7/10
CPC分类号： G11C29/808 , G11C7/1039
摘要： A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.
摘要翻译：存储器件包括：第一主页缓冲器阵列，被配置为访问第一主存储器阵列的数据; 配置为访问第二主存储器阵列的数据的第二主页缓冲器阵列; 冗余页缓冲器阵列，被配置为访问代替所述第一和第二主存储器阵列的冗余存储器阵列的数据; 第一冗余传送单元，被配置为当第一列地址指示第一主存储器阵列的一个或多个缺陷列时，通过第一冗余总线在冗余页缓冲器阵列和存储器件外部之间传送数据; 以及第二冗余传送单元，被配置为当第二列地址指示第二主存储器阵列的一个或多个有缺陷的列时，通过第二冗余总线在冗余页缓冲器阵列和外部之间传送数据。

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