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1. 发明申请

US20130141979A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20130141979A1
公开(公告)日：2013-06-06
申请号：US13599997
申请日：2012-08-30
申请人： Bo Kyeom KIM
发明人： Bo Kyeom KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/06 , G11C16/26
摘要： A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
摘要翻译：一种半导体存储装置，包括锁存单元，配置为响应于复位选择信号的激活而被驱动并且重置第一节点和第二节点; 以及辅助驱动单元，被配置为响应于所述复位选择信号和所述第一节点或所述第二节点的电压逻辑电平来支持所述锁存单元的驱动力，其中所述第一节点和所述第二节点具有基本相反的电压逻辑电平。

2. 发明申请

US20120140573A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20120140573A1
公开(公告)日：2012-06-07
申请号：US13182526
申请日：2011-07-14
申请人： Bo Kyeom KIM
发明人： Bo Kyeom KIM
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1042 , G11C7/1066 , G11C7/1069 , G11C7/222
摘要： A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.
摘要翻译：半导体存储器件包括：页缓冲器，被配置为响应于读命令存储从所选存储器单元接收的数据;第一寄存器，被配置为存储响应于第一控制信号从页缓冲器接收的第一数据;第二寄存器，存储响应于第二控制信号从页缓冲器接收的第二数据，数据I / O电路被配置为分别从第一寄存器或第二寄存器输出第一或第二数据，输入从第一寄存器或第二寄存器接收的第三数据页缓冲器到第一和第二寄存器中的另一个，以及控制逻辑，被配置为在输出第一和第二数据时顺序地提供第一控制信号和第二控制信号。

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