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1. 发明授权

US07276759B1 Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling 失效
标题翻译：具有控制和浮动栅极和侧壁耦合的非易失性电气可变半导体存储器
公开(公告)号：US07276759B1
公开(公告)日：2007-10-02
申请号：US10798138
申请日：2004-03-11
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11519
摘要： In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.
摘要翻译：在存储单元阵列中，每个存储单元包括一个横向设置在浮动栅极附近的控制栅极。每个存储器列中的存储单元设置在单个阱内。控制栅极和浮置栅极设置在两个扩散区域之间。可以通过将电压组合施加到扩散区域，控制栅极和阱来擦除和编程每个存储器单元。

2. 发明申请

US20110121380A1 NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELL FOR STORING MULTIPLE DATA 审中-公开
标题翻译：用于存储多个数据的非易失性电气可变存储器单元
公开(公告)号：US20110121380A1
公开(公告)日：2011-05-26
申请号：US12902614
申请日：2010-10-12
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , H01L27/115 , H01L27/11524 , H01L29/40114 , H01L29/7887
摘要： A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
摘要翻译：一种存储单元，包括一个横向设置在两个浮动栅极之间的控制栅极，每个浮动栅极能够保存数据。存储器单元中的每个浮置栅极可以通过将电压组合施加到扩散区域，控制栅极和阱来被擦除和编程。多个存储器单元产生存储器串，并且存储器阵列由以行和列排列的多个存储器串形成。

3. 发明授权

US07834388B2 Memory array of non-volatile electrically alterable memory cells for storing multiple data 有权
标题翻译：用于存储多个数据的非易失性电可变存储器单元的存储器阵列
公开(公告)号：US07834388B2
公开(公告)日：2010-11-16
申请号：US11348556
申请日：2006-02-06
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , G11C16/0408 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/7887
摘要： A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
摘要翻译：一种存储单元，包括一个横向设置在两个浮动栅极之间的控制栅极，每个浮动栅极能够保存数据。存储器单元中的每个浮置栅极可以通过将电压组合施加到扩散区域，控制栅极和阱来被擦除和编程。多个存储器单元产生存储器串，并且存储器阵列由以行和列排列的多个存储器串形成。

4. 发明授权

US07449744B1 Non-volatile electrically alterable memory cell and use thereof in multi-function memory array 有权
标题翻译：非易失性电可变存储器单元及其在多功能存储器阵列中的应用
公开(公告)号：US07449744B1
公开(公告)日：2008-11-11
申请号：US10910198
申请日：2004-08-03
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L23/62 , H01L29/93
CPC分类号： H01L29/66825 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.
摘要翻译：包括分布在几个DRAM扇区中的DRAM，分布在几个闪存EEPROM扇区中的闪存EEPROM，互连DRAM扇区和闪存EEPROM扇区的数据总线以及多个存储器访问控制电路的多功能存储器阵列。可以独立地访问每个DRAM扇区和闪存EEPROM扇区，并且可以在DRAM扇区和闪存EEPROM扇区之间传输数据。外部数据也可以写入DRAM或闪存EEPROM。一个扇区中的闪存EEPROM分布在行和列中，每个列中的单元格通过深沟槽隔离区域与相邻列中的单元格分离。

5. 发明授权

US5760605A Programmable high speed routing switch 失效
标题翻译：可编程高速路由交换机
公开(公告)号：US5760605A
公开(公告)日：1998-06-02
申请号：US723082
申请日：1996-09-30
申请人： Ying W. Go
发明人： Ying W. Go
IPC分类号： H03K17/06 , H03K17/24 , H03K19/094
CPC分类号： H03K17/063 , H03K17/24
摘要： A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.
摘要翻译：提供了一种可编程的高速布线开关，其具有较低的导通电阻，从而增加其栅极氧化可靠性。路由交换机包括具有浮动门（FG）的非易失性存储单元（12）。浮栅被选择性地充电和放电以提供净正电位或净负电位。路由选择开关还包括存储晶体管（14），栅极晶体管（16）和多重负载元件（18）。存储晶体管的源极连接到第一电源电位。存储晶体管的栅极连接到存储单元的浮置栅极，其漏极连接到栅极晶体管的栅极和多重负载元件的第一端。栅极晶体管的漏极连接到第一信号线（PG1），并且栅极晶体管的源极连接到第二信号线（PG2）。多负载元件的第二端连接到第二电源电位。

6. 发明授权

US07544566B2 Method for manufacturing a non-volatile electrically alterable memory cell that stores multiple data 有权
标题翻译：用于制造存储多个数据的非易失性电可变存储器单元的方法
公开(公告)号：US07544566B2
公开(公告)日：2009-06-09
申请号：US11744730
申请日：2007-05-04
申请人： Andy T. Yu , Ying W. Go
发明人： Andy T. Yu , Ying W. Go
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887 , H01L29/7923
摘要： A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer includes (a) forming an insulating layer on the semiconductor layer, (b) depositing a first conductive layer on the insulating layer, (c) forming trench isolation regions along and into the semiconductor layer, (d) depositing a sacrificial material on the first conductive layer, (e) etching the sacrificial material to form isolation channels, (f) forming two gate masks along lateral sides of the sacrificial material, (g) etching the first conductive layer to extend the channels to the insulating layer, (h) etching the sacrificial material to form a control channel, (i) etching the block of the first conductive layer, and (j) filling the control channel with a second conductive layer.
摘要翻译：用于在半导体层上制造电可变存储器件的自对准方法包括：（a）在半导体层上形成绝缘层，（b）在绝缘层上沉积第一导电层，（c）沿着绝缘层形成沟槽隔离区（d）在第一导电层上沉积牺牲材料，（e）蚀刻牺牲材料以形成隔离通道，（f）沿牺牲材料的侧面形成两个栅极掩模，（g）蚀刻所述第一导电层将所述通道延伸到所述绝缘层，（h）蚀刻所述牺牲材料以形成控制沟道，（i）蚀刻所述第一导电层的所述块，以及（j）用所述第二导电层。

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