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1. 发明授权

US08205324B2 Method of fabricating an inductor structure 有权
标题翻译：制造电感器结构的方法
公开(公告)号：US08205324B2
公开(公告)日：2012-06-26
申请号：US12275599
申请日：2008-11-21
申请人： Peter Smeys , Peter Johnson , Andrei Papou
发明人： Peter Smeys , Peter Johnson , Andrei Papou
IPC分类号： H01F3/00 , H01F41/02
CPC分类号： H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/49005 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49144 , H01L2924/00
摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.
摘要翻译：利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。因此，由电感线圈产生的磁场与硬磁轴平行和自对准。通过在平行于容易轴的施加磁场中电镀来增强易轴。

2. 发明授权

US07936246B2 On-chip inductor for high current applications 有权
标题翻译：用于大电流应用的片上电感
公开(公告)号：US07936246B2
公开(公告)日：2011-05-03
申请号：US11973536
申请日：2007-10-09
申请人： Peter J. Hopper , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Smeys , Andrei Papou
IPC分类号： H01F27/24
CPC分类号： H01F17/0013 , H01F3/14 , H01F27/34 , H01F41/046 , H01F2017/0066 , Y10T29/49078
摘要： Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.
摘要翻译：用于大电流应用的片上电感器的非线性铁磁芯材料的饱和度通过提供其中磁通量不形成闭环但是分成多个子通量的核心设计而显着降低，这些子通量被引导以相互抵消。该设计可实现高电流功率应用的高片内电感。

3. 发明授权

US07897472B2 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
标题翻译：用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
公开(公告)号：US07897472B2
公开(公告)日：2011-03-01
申请号：US12624259
申请日：2009-11-23
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01L21/20
CPC分类号： H01L23/645 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/19015 , H01L2924/19104 , H01L2924/00
摘要： Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.
摘要翻译：描述了在半导体晶片上形成多个电感器的方法。将镀层和光致抗蚀剂层施加在半导体晶片上。使用光刻技术在光致抗蚀剂层中蚀刻凹陷区域，其暴露下面的镀层的部分。将金属电镀到光致抗蚀剂层的凹陷区域中以形成多个磁芯电感器构件。介质绝缘层施加在磁芯电感器部件上。在电介质绝缘层上施加附加的电镀和光致抗蚀剂层。在新施加的光致抗蚀剂层中形成凹陷区域。电镀用于在凹陷区域形成电感线圈。可选地，可以在电感线圈上施加磁性糊。

4. 发明授权

US09024397B2 Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure 有权
标题翻译：绝热微制造原子钟结构及形成原子钟结构的方法
公开(公告)号：US09024397B2
公开(公告)日：2015-05-05
申请号：US13345688
申请日：2012-01-07
申请人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
发明人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
IPC分类号： H01L31/0224 , H01L31/18 , G01R33/02 , G04F5/14 , H01L31/00 , H01L31/103 , H03L7/26
CPC分类号： H01L31/024 , G04F5/14 , H01L31/00 , H01L31/022408 , H01L31/103 , H01L31/18 , H01L31/1804 , H03L7/26 , Y02E10/547
摘要： A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
摘要翻译：微制造的原子钟结构是绝热的，使得原子钟结构可以在外部温度下降到-40℃的环境中以非常小的功率运行，同时保持适当的温度 VCSEL和蒸汽池内的气体的操作。

5. 发明申请

US20130168808A1 MEMS POWER INDUCTOR WITH MAGNETIC LAMINATIONS FORMED IN A CRACK RESISTANT HIGH ASPECT RATIO STRUCTURE 有权
标题翻译：具有抗裂高速比结构形成的具有磁性层压的MEMS功率电感器
公开(公告)号：US20130168808A1
公开(公告)日：2013-07-04
申请号：US13340849
申请日：2011-12-30
申请人： Andrei Papou , William French , Peter J. Hopper
发明人： Andrei Papou , William French , Peter J. Hopper
IPC分类号： H01L29/82 , H01L43/12
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.
摘要翻译：磁性叠层形成在第一非导电结构的开口中，第一非导电结构形成在具有小于第一非导电结构的最大纵横比的最大纵横比的第二非导电结构的开口中。第二非导电结构比第一非导电结构更具抗裂性，从而保护第一非导电结构和磁性层叠免受环境污染物的影响。

6. 发明授权

US08042260B2 Methods of forming inductors on integrated circuits 有权
标题翻译：在集成电路上形成电感器的方法
公开(公告)号：US08042260B2
公开(公告)日：2011-10-25
申请号：US12250385
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.
摘要翻译：所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。第一组间隔开的金属芯元件形成在衬底上。然后在芯元件的侧表面上形成隔离侧壁。之后，在衬底上形成第二组金属芯元件。第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

7. 发明授权

US07584533B2 Method of fabricating an inductor structure on an integrated circuit structure 有权
标题翻译：在集成电路结构上制造电感器结构的方法
公开(公告)号：US07584533B2
公开(公告)日：2009-09-08
申请号：US11973861
申请日：2007-10-10
申请人： Peter Smeys , Peter Johnson , Andrei Papou
发明人： Peter Smeys , Peter Johnson , Andrei Papou
IPC分类号： H01F3/00 , H01F41/02
CPC分类号： H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/49005 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49144 , H01L2924/00
摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.
摘要翻译：利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。因此，由电感线圈产生的磁场与硬磁轴平行和自对准。可以通过在平行于容易轴的施加磁场中电镀来增强易轴。

8. 发明申请

US20090038142A1 METHODS OF FORMING INDUCTORS ON INTEGRATED CIRCUITS 有权
标题翻译：集成电路形成电感的方法
公开(公告)号：US20090038142A1
公开(公告)日：2009-02-12
申请号：US12250385
申请日：2008-10-13
申请人： Peter J. HOPPER , Peter JOHNSON , Peter SMEYS , Andrei PAPOU
发明人： Peter J. HOPPER , Peter JOHNSON , Peter SMEYS , Andrei PAPOU
IPC分类号： H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the forming of a metal seed layer, the deposition and patterning of photoresist, the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.
摘要翻译：所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。第一组间隔开的金属芯元件形成在衬底上。然后在芯元件的侧表面上形成隔离侧壁。之后，在衬底上形成第二组金属芯元件。在一些实施例中，第二组芯元件的至少一个芯元件位于与第一组核心元件相关联的相邻的一对核心元件之间的空间中。第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。具体实施例涉及其它处理操作，例如形成金属种子层，沉积和图案化光致抗蚀剂，选择性地电镀不同类型的金属以形成核心元件和/或沉积和蚀刻掉隔离层以形成核心元件上的隔离侧壁。

9. 发明授权

US09121106B2 Method of forming a laminated magnetic core with sputter deposited and electroplated layers 有权
标题翻译：用溅射沉积和电镀层形成层压磁芯的方法
公开(公告)号：US09121106B2
公开(公告)日：2015-09-01
申请号：US13407352
申请日：2012-02-28
申请人： Dok Won Lee , Andrei Papou , William French , Peter J. Hopper
发明人： Dok Won Lee , Andrei Papou , William French , Peter J. Hopper
IPC分类号： H01L21/00 , C25D7/12 , H01F10/26 , H01F41/26 , C23C14/06 , C23C14/18 , C25D7/00 , H01F3/00 , H01F27/24 , C23C28/00 , H01F41/04
CPC分类号： C25D7/123 , C23C14/0617 , C23C14/185 , C23C28/321 , C23C28/34 , C23C28/42 , C23C28/44 , C25D7/001 , H01F3/00 , H01F10/265 , H01F27/24 , H01F41/046 , H01F41/26
摘要： A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.
摘要翻译：一层叠磁芯，其具有多个磁性层和多个绝缘层，这些绝缘层被布置为使得绝缘层位于每个垂直相邻的一对磁性层之间，以形成具有电镀工艺的磁性层的方法形成，以及具有溅射沉积工艺的绝缘层。

10. 发明授权

US08466537B1 MEMS power inductor with magnetic laminations formed in a crack resistant high aspect ratio structure 有权
标题翻译：具有磁性叠片的MEMS功率电感器形成在耐裂纹高纵横比结构中
公开(公告)号：US08466537B1
公开(公告)日：2013-06-18
申请号：US13340849
申请日：2011-12-30
申请人： Andrei Papou , William French , Peter J. Hopper
发明人： Andrei Papou , William French , Peter J. Hopper
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.
摘要翻译：磁性叠层形成在第一非导电结构的开口中，第一非导电结构形成在具有小于第一非导电结构的最大纵横比的最大纵横比的第二非导电结构的开口中。第二非导电结构比第一非导电结构更具抗裂性，从而保护第一非导电结构和磁性层叠免受环境污染物的影响。

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